From: Vignesh R <vigneshr@ti.com>
To: Marek Vasut <marek.vasut@gmail.com>,
Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Cc: David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Boris Brezillon <boris.brezillon@free-electrons.com>,
Rob Herring <robh+dt@kernel.org>,
linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Vignesh R <vigneshr@ti.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: [RESEND PATCH v2 3/5] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit
Date: Tue, 19 Sep 2017 16:26:03 +0530 [thread overview]
Message-ID: <20170919105605.18533-4-vigneshr@ti.com> (raw)
In-Reply-To: <20170919105605.18533-1-vigneshr@ti.com>
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return clock helps to increase data valid window.
Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit
for boards which do have QSPI return clock provided. Update binding
documentation for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index 7dbe3bd9ac56..bb2075df9b38 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -16,6 +16,9 @@ Required properties:
Optional properties:
- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
+ the read data rather than the QSPI clock. Make sure that QSPI return
+ clock is populated on the board before using this property.
Optional subnodes:
Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
--
2.14.1
next prev parent reply other threads:[~2017-09-19 10:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-19 10:56 [RESEND PATCH v2 0/5] K2G: Add QSPI support Vignesh R
[not found] ` <20170919105605.18533-1-vigneshr-l0cyMroinI0@public.gmane.org>
2017-09-19 10:56 ` [RESEND PATCH v2 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible Vignesh R
2017-09-19 10:56 ` [RESEND PATCH v2 4/5] mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuit Vignesh R
2017-09-19 10:56 ` [RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence Vignesh R
2017-09-22 8:04 ` kbuild test robot
2017-09-22 9:02 ` Vignesh R
2017-09-19 10:56 ` Vignesh R [this message]
2017-09-19 10:56 ` [RESEND PATCH v2 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support Vignesh R
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