* [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC
@ 2017-10-13 7:49 Li Wei
2017-10-13 7:49 ` [PATCH v4 1/5] scsi: ufs: add Hisilicon ufs driver code Li Wei
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Li Wei @ 2017-10-13 7:49 UTC (permalink / raw)
To: robh+dt, mark.rutland, xuwei5, catalin.marinas, will.deacon,
vinholikatti, jejb, martin.petersen, khilman, arnd,
gregory.clement, thomas.petazzoni, yamada.masahiro, riku.voipio,
treding, krzk, eric, devicetree, linux-kernel, linux-arm-kernel,
linux-scsi
Cc: fengbaopeng, wangyupeng4, liwei213, guodong.xu, lihuan41
This patchset adds driver support for UFS for Hi3660 SoC. It is verified on HiKey960 board.
Li Wei (5):
scsi: ufs: add Hisilicon ufs driver code
dt-bindings: scsi: ufs: add document for hisi-ufs
arm64: dts: add ufs dts node
arm64: defconfig: enable configs for Hisilicon ufs
arm64: defconfig: enable f2fs and squashfs
Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 47 ++
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 5 +
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 19 +
arch/arm64/configs/defconfig | 11 +
drivers/scsi/ufs/Kconfig | 9 +
drivers/scsi/ufs/Makefile | 1 +
drivers/scsi/ufs/ufs-hisi.c | 625 +++++++++++++++++++++
drivers/scsi/ufs/ufs-hisi.h | 161 ++++++
8 files changed, 878 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
create mode 100644 drivers/scsi/ufs/ufs-hisi.c
create mode 100644 drivers/scsi/ufs/ufs-hisi.h
--
2.11.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v4 1/5] scsi: ufs: add Hisilicon ufs driver code 2017-10-13 7:49 [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC Li Wei @ 2017-10-13 7:49 ` Li Wei 2017-10-13 7:49 ` [PATCH v4 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs Li Wei ` (3 subsequent siblings) 4 siblings, 0 replies; 9+ messages in thread From: Li Wei @ 2017-10-13 7:49 UTC (permalink / raw) To: robh+dt, mark.rutland, xuwei5, catalin.marinas, will.deacon, vinholikatti, jejb, martin.petersen, khilman, arnd, gregory.clement, thomas.petazzoni, yamada.masahiro, riku.voipio, treding, krzk, eric, devicetree, linux-kernel, linux-arm-kernel, linux-scsi Cc: guodong.xu, liwei213, fengbaopeng, lihuan41, wangyupeng4 add Hisilicon ufs driver code. Signed-off-by: Li Wei <liwei213@huawei.com> Signed-off-by: Geng Jianfeng <gengjianfeng@hisilicon.com> Signed-off-by: Zang Leigang <zangleigang@hisilicon.com> Signed-off-by: Yu Jianfeng <steven.yujianfeng@hisilicon.com> --- drivers/scsi/ufs/Kconfig | 9 + drivers/scsi/ufs/Makefile | 1 + drivers/scsi/ufs/ufs-hisi.c | 625 ++++++++++++++++++++++++++++++++++++++++++++ drivers/scsi/ufs/ufs-hisi.h | 161 ++++++++++++ 4 files changed, 796 insertions(+) create mode 100644 drivers/scsi/ufs/ufs-hisi.c create mode 100644 drivers/scsi/ufs/ufs-hisi.h diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig index e27b4d4e6ae2..bf2ff5628b15 100644 --- a/drivers/scsi/ufs/Kconfig +++ b/drivers/scsi/ufs/Kconfig @@ -80,6 +80,15 @@ config SCSI_UFSHCD_PLATFORM If unsure, say N. +config SCSI_UFS_HISI + tristate "Hisilicon specific hooks to UFS controller platform driver" + depends on (ARCH_HISI || COMPILE_TEST) && SCSI_UFSHCD_PLATFORM + ---help--- + This selects the Hisilicon specific additions to UFSHCD platform driver. + + Select this if you have UFS controller on Hisilicon chipset. + If unsure, say N. + config SCSI_UFS_DWC_TC_PLATFORM tristate "DesignWare platform support using a G210 Test Chip" depends on SCSI_UFSHCD_PLATFORM diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile index 6e77cb0bfee9..9f2c17029a38 100644 --- a/drivers/scsi/ufs/Makefile +++ b/drivers/scsi/ufs/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o +obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c new file mode 100644 index 000000000000..8b7aea2d44c5 --- /dev/null +++ b/drivers/scsi/ufs/ufs-hisi.c @@ -0,0 +1,625 @@ +/* + * + * HiSilicon Hixxxx UFS Driver + * + * Copyright (c) 2016-2017 Linaro Ltd. + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/gpio.h> +#include <linux/time.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_gpio.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include "ufshcd.h" +#include "ufshcd-pltfrm.h" +#include "unipro.h" +#include "ufs-hisi.h" +#include "ufshci.h" + +static int ufs_hisi_check_hibern8(struct ufs_hba *hba) +{ + int err; + u32 tx_fsm_val_0; + u32 tx_fsm_val_1; + unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); + + do { + err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), + &tx_fsm_val_0); + err |= ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); + if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 && + tx_fsm_val_1 == TX_FSM_HIBERN8)) + break; + + /* sleep for max. 200us */ + usleep_range(100, 200); + } while (time_before(jiffies, timeout)); + + /* + * we might have scheduled out for long during polling so + * check the state again. + */ + if (time_after(jiffies, timeout)) { + err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), + &tx_fsm_val_0); + err |= ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); + } + + if (err) { + dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", + __func__, err); + } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 || + tx_fsm_val_1 != TX_FSM_HIBERN8) { + err = -1; + dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", + __func__, tx_fsm_val_0, tx_fsm_val_1); + } + + return err; +} + +static void ufs_hisi_clk_init(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN) + mdelay(1); + /* use abb clk */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL); + ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN); + /* open mphy ref clk */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); +} + +static void ufs_hisi_soc_init(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + u32 reg; + + if (!IS_ERR(host->rst)) + reset_control_assert(host->rst); + + /* HC_PSW powerup */ + ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL); + udelay(10); + /* notify PWR ready */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL); + ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0, + UFS_DEVICE_RESET_CTRL); + + if (gpio_is_valid(host->reset_gpio)) + gpio_direction_output(host->reset_gpio, 0); + + reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL); + reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK; + /* set cfg clk freq */ + ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL); + /* set ref clk freq */ + ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL); + /* bypass ufs clk gate */ + ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS, + CLOCK_GATE_BYPASS); + ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL); + + /* open psw clk */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL); + /* disable ufshc iso */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL); + /* disable phy iso */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN); + /* notice iso disable */ + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL); + + if (!IS_ERR(host->assert)) + reset_control_deassert(host->assert); + + /* disable lp_reset_n */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN); + mdelay(1); + + if (gpio_is_valid(host->reset_gpio)) + gpio_direction_output(host->reset_gpio, 1); + + ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET, + UFS_DEVICE_RESET_CTRL); + + msleep(20); + + /* + * enable the fix of linereset recovery, + * and enable rx_reset/tx_rest beat + * enable ref_clk_en override(bit5) & + * override value = 1(bit4), with mask + */ + ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL); + + if (!IS_ERR(host->rst)) + reset_control_deassert(host->rst); +} + +static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba) +{ + int err; + uint32_t value; + uint32_t reg; + + /* Unipro VS_mphy_disable */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1); + /* PA_HSSeries */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2); + /* MPHY CBRATESEL */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1); + /* MPHY CBOVRCTRL2 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D); + /* MPHY CBOVRCTRL3 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); + /* Unipro VS_MphyCfgUpdt */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + /* MPHY RXOVRCTRL4 rx0 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58); + /* MPHY RXOVRCTRL4 rx1 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58); + /* MPHY RXOVRCTRL5 rx0 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB); + /* MPHY RXOVRCTRL5 rx1 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB); + /* MPHY RXSQCONTROL rx0 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1); + /* MPHY RXSQCONTROL rx1 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1); + /* Unipro VS_MphyCfgUpdt */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + /* Gear3 Synclength */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4A); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4A); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4A); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4A); + /* Tactive RX */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7); + /* Thibernate Tx */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5); + + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + /* Unipro VS_mphy_disable */ + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value); + if (value != 0x1) + dev_info(hba->dev, + "Warring!!! Unipro VS_mphy_disable is 0x%x\n", value); + + /* Unipro VS_mphy_disable */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0); + err = ufs_hisi_check_hibern8(hba); + if (err) + dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n"); + + ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV); + + /* disable auto H8 */ + reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); + reg = reg & (~UFS_AHIT_AH8ITV_MASK); + ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); + + /* Unipro PA_Local_TX_LCC_Enable */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x155E, 0x0), 0x0); + /* close Unipro VS_Mk2ExtnSupport */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0); + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value); + if (value != 0) { + /* Ensure close success */ + dev_info(hba->dev, "WARN: close VS_Mk2ExtnSupport failed\n"); + } + + return err; +} + +static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + /* Unipro DL_AFC0CreditThreshold */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0); + /* Unipro DL_TC0OutAckThreshold */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0); + /* Unipro DL_TC0TXFCThreshold */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9); + + /* not bypass ufs clk gate */ + ufs_sys_ctrl_clr_bits(host, MASK_UFS_CLK_GATE_BYPASS, + CLOCK_GATE_BYPASS); + ufs_sys_ctrl_clr_bits(host, MASK_UFS_SYSCRTL_BYPASS, + UFS_SYSCTRL); + + return 0; +} + +static int ufs_hisi_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + int err = 0; + + switch (status) { + case PRE_CHANGE: + err = ufs_hisi_link_startup_pre_change(hba); + break; + case POST_CHANGE: + err = ufs_hisi_link_startup_post_change(hba); + break; + default: + break; + } + + return err; +} + +struct ufs_hisi_dev_params { + u32 pwm_rx_gear; /* pwm rx gear to work in */ + u32 pwm_tx_gear; /* pwm tx gear to work in */ + u32 hs_rx_gear; /* hs rx gear to work in */ + u32 hs_tx_gear; /* hs tx gear to work in */ + u32 rx_lanes; /* number of rx lanes */ + u32 tx_lanes; /* number of tx lanes */ + u32 rx_pwr_pwm; /* rx pwm working pwr */ + u32 tx_pwr_pwm; /* tx pwm working pwr */ + u32 rx_pwr_hs; /* rx hs working pwr */ + u32 tx_pwr_hs; /* tx hs working pwr */ + u32 hs_rate; /* rate A/B to work in HS */ + u32 desired_working_mode; +}; + +static int ufs_hisi_get_pwr_dev_param( + struct ufs_hisi_dev_params *hisi_param, + struct ufs_pa_layer_attr *dev_max, + struct ufs_pa_layer_attr *agreed_pwr) +{ + int min_hisi_gear; + int min_dev_gear; + bool is_dev_sup_hs = false; + bool is_hisi_max_hs = false; + + if (dev_max->pwr_rx == FASTAUTO_MODE || dev_max->pwr_rx == FAST_MODE) + is_dev_sup_hs = true; + + if (hisi_param->desired_working_mode == FAST) { + is_hisi_max_hs = true; + min_hisi_gear = min_t(u32, hisi_param->hs_rx_gear, + hisi_param->hs_tx_gear); + } else { + min_hisi_gear = min_t(u32, hisi_param->pwm_rx_gear, + hisi_param->pwm_tx_gear); + } + + /* + * device doesn't support HS but + * hisi_param->desired_working_mode is HS, + * thus device and hisi_param don't agree + */ + if (!is_dev_sup_hs && is_hisi_max_hs) { + pr_err("%s: device not support HS\n", __func__); + return -ENOTSUPP; + } else if (is_dev_sup_hs && is_hisi_max_hs) { + /* + * since device supports HS, it supports FAST_MODE. + * since hisi_param->desired_working_mode is also HS + * then final decision (FAST/FASTAUTO) is done according + * to hisi_params as it is the restricting factor + */ + agreed_pwr->pwr_rx = agreed_pwr->pwr_tx = + hisi_param->rx_pwr_hs; + } else { + /* + * here hisi_param->desired_working_mode is PWM. + * it doesn't matter whether device supports HS or PWM, + * in both cases hisi_param->desired_working_mode will + * determine the mode + */ + agreed_pwr->pwr_rx = agreed_pwr->pwr_tx = + hisi_param->rx_pwr_pwm; + } + + /* + * we would like tx to work in the minimum number of lanes + * between device capability and vendor preferences. + * the same decision will be made for rx + */ + agreed_pwr->lane_tx = + min_t(u32, dev_max->lane_tx, hisi_param->tx_lanes); + agreed_pwr->lane_rx = + min_t(u32, dev_max->lane_rx, hisi_param->rx_lanes); + + /* device maximum gear is the minimum between device rx and tx gears */ + min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx); + + /* + * if both device capabilities and vendor pre-defined preferences are + * both HS or both PWM then set the minimum gear to be the chosen + * working gear. + * if one is PWM and one is HS then the one that is PWM get to decide + * what is the gear, as it is the one that also decided previously what + * pwr the device will be configured to. + */ + if ((is_dev_sup_hs && is_hisi_max_hs) || + (!is_dev_sup_hs && !is_hisi_max_hs)) + agreed_pwr->gear_rx = agreed_pwr->gear_tx = + min_t(u32, min_dev_gear, min_hisi_gear); + else + agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_hisi_gear; + + agreed_pwr->hs_rate = hisi_param->hs_rate; + + pr_info("ufs final power mode: gear = %d, lane = %d, pwr = %d, rate = %d\n", + agreed_pwr->gear_rx, agreed_pwr->lane_rx, agreed_pwr->pwr_rx, + agreed_pwr->hs_rate); + return 0; +} + +static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba) +{ + /* update */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1); + /* PA_TxSkip */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0); + /*PA_PWRModeUserData0 = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191); + /*PA_PWRModeUserData1 = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535); + /*PA_PWRModeUserData2 = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767); + /*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191); + /*DME_TC0ReplayTimeOutVal = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535); + /*DME_AFC0ReqTimeOutVal = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767); + /*PA_PWRModeUserData3 = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191); + /*PA_PWRModeUserData4 = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535); + /*PA_PWRModeUserData5 = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767); + /*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191); + /*DME_TC1ReplayTimeOutVal = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535); + /*DME_AFC1ReqTimeOutVal = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767); +} + +static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, + struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) +{ + struct ufs_hisi_dev_params ufs_hisi_cap; + int ret = 0; + uint32_t value; + + if (!dev_req_params) { + dev_err(hba->dev, + "%s: incoming dev_req_params is NULL\n", __func__); + ret = -EINVAL; + goto out; + } + + switch (status) { + case PRE_CHANGE: + ufs_hisi_cap.rx_lanes = UFS_HISI_LIMIT_NUM_LANES_RX; + ufs_hisi_cap.tx_lanes = UFS_HISI_LIMIT_NUM_LANES_TX; + ufs_hisi_cap.hs_rx_gear = UFS_HISI_LIMIT_HSGEAR_RX; + ufs_hisi_cap.hs_tx_gear = UFS_HISI_LIMIT_HSGEAR_TX; + ufs_hisi_cap.pwm_rx_gear = UFS_HISI_LIMIT_PWMGEAR_RX; + ufs_hisi_cap.pwm_tx_gear = UFS_HISI_LIMIT_PWMGEAR_TX; + ufs_hisi_cap.rx_pwr_pwm = UFS_HISI_LIMIT_RX_PWR_PWM; + ufs_hisi_cap.tx_pwr_pwm = UFS_HISI_LIMIT_TX_PWR_PWM; + ufs_hisi_cap.rx_pwr_hs = UFS_HISI_LIMIT_RX_PWR_HS; + ufs_hisi_cap.tx_pwr_hs = UFS_HISI_LIMIT_TX_PWR_HS; + ufs_hisi_cap.hs_rate = UFS_HISI_LIMIT_HS_RATE; + ufs_hisi_cap.desired_working_mode = UFS_HISI_LIMIT_DESIRED_MODE; + + ret = ufs_hisi_get_pwr_dev_param( + &ufs_hisi_cap, dev_max_params, dev_req_params); + if (ret) { + dev_err(hba->dev, + "%s: failed to determine capabilities\n", __func__); + goto out; + } + + dev_info(hba->dev, "set TX_EQUALIZER 3.5db\n"); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0037, 0x0), 0x1); + if ((dev_req_params->lane_tx > 1) && + (dev_req_params->lane_rx > 1)) + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0037, 0x1), 0x1); + + ufs_hisi_pwr_change_pre_change(hba); + break; + case POST_CHANGE: + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x0037, 0x0), &value); + dev_info(hba->dev, + "check TX_EQUALIZER DB value lane0 = 0x%x\n", value); + if ((dev_req_params->lane_tx > 1) && + (dev_req_params->lane_rx > 1)) { + ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(0x0037, 0x1), &value); + dev_info(hba->dev, + "TX_EQUALIZER DB value lane1 = 0x%x\n", value); + } + break; + default: + ret = -EINVAL; + break; + } +out: + return ret; +} + +static int ufs_hisi_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + if (ufshcd_is_runtime_pm(pm_op)) + return 0; + + if (host->in_suspend) { + WARN_ON(1); + return 0; + } + + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + udelay(10); + /* set ref_dig_clk override of PHY PCS to 0 */ + ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL); + + host->in_suspend = true; + + return 0; +} + +static int ufs_hisi_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + if (!host->in_suspend) + return 0; + + /* set ref_dig_clk override of PHY PCS to 1 */ + ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL); + udelay(10); + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + + host->in_suspend = false; + return 0; +} + +static int ufs_hisi_get_resource(struct ufs_hisi_host *host) +{ + struct resource *mem_res; + struct device *dev = host->hba->dev; + struct platform_device *pdev = to_platform_device(dev); + + /* get resource of ufs sys ctrl */ + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + host->ufs_sys_ctrl = devm_ioremap_resource(dev, mem_res); + + if (IS_ERR(host->ufs_sys_ctrl)) + return PTR_ERR(host->ufs_sys_ctrl); + + host->rst = devm_reset_control_get(dev, "rst"); + host->assert = devm_reset_control_get(dev, "assert"); + + return 0; +} + +static void ufs_hisi_set_pm_lvl(struct ufs_hba *hba) +{ + hba->rpm_lvl = UFS_PM_LVL_1; + hba->spm_lvl = UFS_PM_LVL_3; +} + +/** + * ufs_hisi_init + * @hba: host controller instance + */ +static int ufs_hisi_init(struct ufs_hba *hba) +{ + int err; + struct device *dev = hba->dev; + struct ufs_hisi_host *host; + + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); + if (!host) + return -ENOMEM; + + host->hba = hba; + ufshcd_set_variant(hba, host); + + host->reset_gpio = of_get_named_gpio(hba->dev->of_node, + "reset-gpio", 0); + if (gpio_is_valid(host->reset_gpio)) { + err = devm_gpio_request_one(dev, host->reset_gpio, + GPIOF_DIR_OUT, "hisi_ufs_reset"); + if (err) + dev_err(dev, "could not acquire gpio (err=%d)\n", err); + } + + ufs_hisi_set_pm_lvl(hba); + + err = ufs_hisi_get_resource(host); + if (err) { + ufshcd_set_variant(hba, NULL); + return err; + } + + ufs_hisi_clk_init(hba); + + ufs_hisi_soc_init(hba); + + return 0; +} + +static struct ufs_hba_variant_ops ufs_hba_hisi_vops = { + .name = "hisi", + .init = ufs_hisi_init, + .link_startup_notify = ufs_hisi_link_startup_notify, + .pwr_change_notify = ufs_hisi_pwr_change_notify, + .suspend = ufs_hisi_suspend, + .resume = ufs_hisi_resume, +}; + +static int ufs_hisi_probe(struct platform_device *pdev) +{ + return ufshcd_pltfrm_init(pdev, &ufs_hba_hisi_vops); +} + +static int ufs_hisi_remove(struct platform_device *pdev) +{ + struct ufs_hba *hba = platform_get_drvdata(pdev); + + ufshcd_remove(hba); + return 0; +} + +static const struct of_device_id ufs_hisi_of_match[] = { + { .compatible = "hisilicon,hi3660-ufs" }, + {}, +}; + +static const struct dev_pm_ops ufs_hisi_pm_ops = { + .suspend = ufshcd_pltfrm_suspend, + .resume = ufshcd_pltfrm_resume, + .runtime_suspend = ufshcd_pltfrm_runtime_suspend, + .runtime_resume = ufshcd_pltfrm_runtime_resume, + .runtime_idle = ufshcd_pltfrm_runtime_idle, +}; + +static struct platform_driver ufs_hisi_pltform = { + .probe = ufs_hisi_probe, + .remove = ufs_hisi_remove, + .shutdown = ufshcd_pltfrm_shutdown, + .driver = { + .name = "ufshcd-hisi", + .pm = &ufs_hisi_pm_ops, + .of_match_table = of_match_ptr(ufs_hisi_of_match), + }, +}; +module_platform_driver(ufs_hisi_pltform); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:ufshcd-hisi"); +MODULE_DESCRIPTION("HiSilicon Hixxxx UFS Driver"); diff --git a/drivers/scsi/ufs/ufs-hisi.h b/drivers/scsi/ufs/ufs-hisi.h new file mode 100644 index 000000000000..c2cf5830d26c --- /dev/null +++ b/drivers/scsi/ufs/ufs-hisi.h @@ -0,0 +1,161 @@ +/* Copyright (c) 2017, HiSilicon. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef UFS_HISI_H_ +#define UFS_HISI_H_ + +#define HBRN8_POLL_TOUT_MS 1000 + +/* + * pericrg specific define + */ +#define PEREN5_OFFSET (0x050) +#define PERRSTEN3_OFFSET (0x084) +#define PERRSTDIS3_OFFSET (0x088) +#define PERRSTSTAT3_OFFSET (0x08C) +#define CLKDIV16_OFFSET (0x0E8) +#define CLKDIV17_OFFSET (0x0EC) +#define CLKDIV21_OFFSET (0x0FC) +#define UFS_ARESET UFS_BIT(7) +#define RST_UFS UFS_BIT(12) + +/* + * ufs sysctrl specific define + */ +#define PSW_POWER_CTRL (0x04) +#define PHY_ISO_EN (0x08) +#define HC_LP_CTRL (0x0C) +#define PHY_CLK_CTRL (0x10) +#define PSW_CLK_CTRL (0x14) +#define CLOCK_GATE_BYPASS (0x18) +#define RESET_CTRL_EN (0x1C) +#define PHY_RESET_STATUS (0x28) +#define UFS_SYSCTRL (0x5C) +#define UFS_DEVICE_RESET_CTRL (0x60) +#define UFS_APB_ADDR_MASK (0x64) + +#define BIT_UFS_PSW_ISO_CTRL (1 << 16) +#define BIT_UFS_PSW_MTCMOS_EN (1 << 0) +#define BIT_UFS_REFCLK_ISO_EN (1 << 16) +#define BIT_UFS_PHY_ISO_CTRL (1 << 0) +#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) +#define BIT_SYSCTRL_LP_PWR_GATE (1 << 0) +#define BIT_SYSCTRL_PWR_READY (1 << 8) +#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) +#define MASK_SYSCTRL_REF_CLOCK_SEL (0x3 << 8) +#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) +#define UFS_FREQ_CFG_CLK (0x39) +#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) +#define MASK_UFS_CLK_GATE_BYPASS (0x3F) +#define BIT_STATUS_LP_RESETCOMPLETE (1 << 0) +#define BIT_SYSCTRL_LP_RESET_N (1 << 0) +#define BIT_UFS_REFCLK_SRC_SEl (1 << 0) +#define MASK_UFS_SYSCRTL_BYPASS (0x3F << 16) +#define MASK_UFS_DEVICE_RESET (0x1 << 16) +#define BIT_UFS_DEVICE_RESET (0x1) + +/* + * M-TX Configuration Attributes for Hixxxx + */ +#define MPHY_TX_FSM_STATE 0x41 +#define TX_FSM_DISABLED 0x0 +#define TX_FSM_HIBERN8 0x1 +#define TX_FSM_SLEEP 0x2 +#define TX_FSM_STALL 0x3 +#define TX_FSM_LS_BURST 0x4 +#define TX_FSM_HS_BURST 0x5 +#define TX_FSM_LINE_CFG 0x6 +#define TX_FSM_LINE_RESET 0x7 + +/* + * Hixxxx UFS HC specific Registers + */ +enum { + UFS_REG_OCPTHRTL = 0xc0, + UFS_REG_OOCPR = 0xc4, + + UFS_REG_CDACFG = 0xd0, + UFS_REG_CDATX1 = 0xd4, + UFS_REG_CDATX2 = 0xd8, + UFS_REG_CDARX1 = 0xdc, + UFS_REG_CDARX2 = 0xe0, + UFS_REG_CDASTA = 0xe4, + + UFS_REG_LBMCFG = 0xf0, + UFS_REG_LBMSTA = 0xf4, + UFS_REG_UFSMODE = 0xf8, + + UFS_REG_HCLKDIV = 0xfc, +}; + +/* AHIT - Auto-Hibernate Idle Timer */ +#define UFS_AHIT_AH8ITV_MASK 0x3FF + +#define UFS_AHIT_AUTOH8_TIMER (0x1001) + +/* REG UFS_REG_OCPTHRTL definition */ +#define LP_PGE UFS_BIT(16) +#define LP_AH8_PGE UFS_BIT(17) + +#define UFS_HCLKDIV_NORMAL_VALUE 0xE4 +#define UFS_HCLKDIV_FPGA_VALUE 0x28 + +/* Hixxxx UFS Unipro specific Registers */ +#define VS_ULPH8_Cntrl 0xd0af +#define Ulp_Ulp_CtrlMode UFS_BIT(3) + +/* vendor specific pre-defined parameters */ +#define SLOW 1 +#define FAST 2 + +#define UFS_HISI_LIMIT_NUM_LANES_RX 2 +#define UFS_HISI_LIMIT_NUM_LANES_TX 2 +#define UFS_HISI_LIMIT_HSGEAR_RX UFS_HS_G3 +#define UFS_HISI_LIMIT_HSGEAR_TX UFS_HS_G3 +#define UFS_HISI_LIMIT_PWMGEAR_RX UFS_PWM_G1 +#define UFS_HISI_LIMIT_PWMGEAR_TX UFS_PWM_G1 +#define UFS_HISI_LIMIT_RX_PWR_PWM SLOWAUTO_MODE +#define UFS_HISI_LIMIT_TX_PWR_PWM SLOWAUTO_MODE +#define UFS_HISI_LIMIT_RX_PWR_HS FAST_MODE +#define UFS_HISI_LIMIT_TX_PWR_HS FAST_MODE +#define UFS_HISI_LIMIT_HS_RATE PA_HS_MODE_B +#define UFS_HISI_LIMIT_DESIRED_MODE FAST + +struct ufs_hisi_host { + struct ufs_hba *hba; + void __iomem *ufs_sys_ctrl; + struct reset_control *rst; + struct reset_control *assert; + + int avail_ln_rx; + int avail_ln_tx; + + u32 busthrtl_backup; + u32 reset_gpio; + + bool in_suspend; + + struct ufs_pa_layer_attr dev_req_params; +}; + +#define ufs_sys_ctrl_writel(host, val, reg) \ + writel((val), (host)->ufs_sys_ctrl + (reg)) +#define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg)) +#define ufs_sys_ctrl_set_bits(host, mask, reg) \ + ufs_sys_ctrl_writel( \ + (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg)) +#define ufs_sys_ctrl_clr_bits(host, mask, reg) \ + ufs_sys_ctrl_writel((host), \ + ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \ + (reg)) +#endif /* UFS_HISI_H_ */ -- 2.11.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs 2017-10-13 7:49 [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC Li Wei 2017-10-13 7:49 ` [PATCH v4 1/5] scsi: ufs: add Hisilicon ufs driver code Li Wei @ 2017-10-13 7:49 ` Li Wei [not found] ` <20171013074936.97284-3-liwei213-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2017-10-13 7:49 ` [PATCH v4 3/5] arm64: dts: add ufs dts node Li Wei ` (2 subsequent siblings) 4 siblings, 1 reply; 9+ messages in thread From: Li Wei @ 2017-10-13 7:49 UTC (permalink / raw) To: robh+dt, mark.rutland, xuwei5, catalin.marinas, will.deacon, vinholikatti, jejb, martin.petersen, khilman, arnd, gregory.clement, thomas.petazzoni, yamada.masahiro, riku.voipio, treding, krzk, eric, devicetree, linux-kernel, linux-arm-kernel, linux-scsi Cc: guodong.xu, liwei213, fengbaopeng, lihuan41, wangyupeng4 add ufs node document for Hisilicon. Signed-off-by: Li Wei <liwei213@huawei.com> --- Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt new file mode 100644 index 000000000000..ee114a65143d --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt @@ -0,0 +1,47 @@ +* Hisilicon Universal Flash Storage (UFS) Host Controller + +UFS nodes are defined to describe on-chip UFS hardware macro. +Each UFS Host Controller should have its own node. + +Required properties: +- compatible : compatible list, contains one of the following - + "hisilicon,hi3660-ufs" for hisi ufs host controller + present on Hi3660 chipset. +- reg : should contain UFS register address space & UFS SYS CTRL register address, +- interrupt-parent : interrupt device +- interrupts : interrupt number +- clocks : List of phandle and clock specifier pairs +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. "clk_ref", "clk_phy" is optional +- resets : reset node register, one reset the clk and the other reset the controller +- reset-names : describe reset node register + +Optional properties for board device: +- reset-gpio : specifies to reset devices + +Example: + + ufs: ufs@ff3b0000 { + compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; + /* 0: HCI standard */ + /* 1: UFS SYS CTRL */ + reg = <0x0 0xff3b0000 0x0 0x1000>, + <0x0 0xff3b1000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; + clock-names = "clk_ref", "clk_phy"; + freq-table-hz = <0 0>, <0 0>; + /* offset: 0x84; bit: 12 */ + /* offset: 0x84; bit: 7 */ + resets = <&crg_rst 0x84 12>, + <&crg_rst 0x84 7>; + reset-names = "rst", "assert"; + }; + + &ufs { + reset-gpio = <&gpio18 1 0>; + status = "okay"; + }; + -- 2.11.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
[parent not found: <20171013074936.97284-3-liwei213-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH v4 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs [not found] ` <20171013074936.97284-3-liwei213-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> @ 2017-10-17 21:17 ` Rob Herring 2017-10-18 10:23 ` 答复: " liwei (CM) 0 siblings, 1 reply; 9+ messages in thread From: Rob Herring @ 2017-10-17 21:17 UTC (permalink / raw) To: Li Wei Cc: mark.rutland-5wv7dgnIgG8, xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8, vinholikatti-Re5JQEeQqe8AvxtiuMwx3w, jejb-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8, martin.petersen-QHcLZuEGTsvQT0dZR+AlfA, khilman-rdvid1DuHRBWk0Htik3J/w, arnd-r2nGTMty4D4, gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A, riku.voipio-QSEj5FYQhm4dnm+yROfE0A, treding-DDmLM1+adcrQT0dZR+AlfA, krzk-DgEjT+Ai2ygdnm+yROfE0A, eric-WhKQ6XTQaPysTnJN9+BGXg, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-scsi-u79uwXL29TY76Z2rM5mHXA, guodong.xu-QSEj5FYQhm4dnm+yROfE0A, fengbaopeng-C8/M+/jPZTeaMJb+Lgu22Q, lihuan41-C8/M+/jPZTeaMJb+Lgu22Q, wangyupeng4-C8/M+/jPZTeaMJb+Lgu22Q On Fri, Oct 13, 2017 at 03:49:33PM +0800, Li Wei wrote: > add ufs node document for Hisilicon. > > Signed-off-by: Li Wei <liwei213-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> > --- > Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 47 ++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt > > diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt > new file mode 100644 > index 000000000000..ee114a65143d > --- /dev/null > +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt > @@ -0,0 +1,47 @@ > +* Hisilicon Universal Flash Storage (UFS) Host Controller > + > +UFS nodes are defined to describe on-chip UFS hardware macro. > +Each UFS Host Controller should have its own node. > + > +Required properties: > +- compatible : compatible list, contains one of the following - > + "hisilicon,hi3660-ufs" for hisi ufs host controller > + present on Hi3660 chipset. > +- reg : should contain UFS register address space & UFS SYS CTRL register address, > +- interrupt-parent : interrupt device > +- interrupts : interrupt number > +- clocks : List of phandle and clock specifier pairs > +- clock-names : List of clock input name strings sorted in the same > + order as the clocks property. "clk_ref", "clk_phy" is optional > +- resets : reset node register, one reset the clk and the other reset the controller > +- reset-names : describe reset node register > + > +Optional properties for board device: > +- reset-gpio : specifies to reset devices Should be "reset-gpios". > + > +Example: > + > + ufs: ufs@ff3b0000 { > + compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; > + /* 0: HCI standard */ > + /* 1: UFS SYS CTRL */ > + reg = <0x0 0xff3b0000 0x0 0x1000>, > + <0x0 0xff3b1000 0x0 0x1000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, > + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; > + clock-names = "clk_ref", "clk_phy"; > + freq-table-hz = <0 0>, <0 0>; > + /* offset: 0x84; bit: 12 */ > + /* offset: 0x84; bit: 7 */ > + resets = <&crg_rst 0x84 12>, > + <&crg_rst 0x84 7>; > + reset-names = "rst", "assert"; > + }; > + > + &ufs { > + reset-gpio = <&gpio18 1 0>; > + status = "okay"; Don't show status or the chip/board split in examples. > + }; > + > -- > 2.11.0 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 9+ messages in thread
* 答复: [PATCH v4 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs 2017-10-17 21:17 ` Rob Herring @ 2017-10-18 10:23 ` liwei (CM) 0 siblings, 0 replies; 9+ messages in thread From: liwei (CM) @ 2017-10-18 10:23 UTC (permalink / raw) To: Rob Herring Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, eric@anholt.net, krzk@kernel.org, lihuan (Z), vinholikatti@gmail.com, jejb@linux.vnet.ibm.com, linux-scsi@vger.kernel.org, khilman@baylibre.com, xuwei (O), treding@nvidia.com, devicetree@vger.kernel.org, arnd@arndb.de, Fengbaopeng (kevin, Kirin Solution Dept), gregory.clement@free-electrons.com, linux-arm-kernel@lists.infradead.org, wangyupe Hi, Rob Thanks for your review, I will fix them in patch v5. -----邮件原件----- 发件人: Rob Herring [mailto:robh@kernel.org] 发送时间: 2017年10月18日 5:18 收件人: liwei (CM) 抄送: mark.rutland@arm.com; xuwei (O); catalin.marinas@arm.com; will.deacon@arm.com; vinholikatti@gmail.com; jejb@linux.vnet.ibm.com; martin.petersen@oracle.com; khilman@baylibre.com; arnd@arndb.de; gregory.clement@free-electrons.com; thomas.petazzoni@free-electrons.com; yamada.masahiro@socionext.com; riku.voipio@linaro.org; treding@nvidia.com; krzk@kernel.org; eric@anholt.net; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-scsi@vger.kernel.org; guodong.xu@linaro.org; Fengbaopeng (kevin, Kirin Solution Dept); lihuan (Z); wangyupeng (A) 主题: Re: [PATCH v4 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs On Fri, Oct 13, 2017 at 03:49:33PM +0800, Li Wei wrote: > add ufs node document for Hisilicon. > > Signed-off-by: Li Wei <liwei213@huawei.com> > --- > Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 47 ++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt > > diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt > new file mode 100644 > index 000000000000..ee114a65143d > --- /dev/null > +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt > @@ -0,0 +1,47 @@ > +* Hisilicon Universal Flash Storage (UFS) Host Controller > + > +UFS nodes are defined to describe on-chip UFS hardware macro. > +Each UFS Host Controller should have its own node. > + > +Required properties: > +- compatible : compatible list, contains one of the following - > + "hisilicon,hi3660-ufs" for hisi ufs host controller > + present on Hi3660 chipset. > +- reg : should contain UFS register address space & UFS SYS CTRL register address, > +- interrupt-parent : interrupt device > +- interrupts : interrupt number > +- clocks : List of phandle and clock specifier pairs > +- clock-names : List of clock input name strings sorted in the same > + order as the clocks property. "clk_ref", "clk_phy" is optional > +- resets : reset node register, one reset the clk and the other reset the controller > +- reset-names : describe reset node register > + > +Optional properties for board device: > +- reset-gpio : specifies to reset devices Should be "reset-gpios". > + > +Example: > + > + ufs: ufs@ff3b0000 { > + compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; > + /* 0: HCI standard */ > + /* 1: UFS SYS CTRL */ > + reg = <0x0 0xff3b0000 0x0 0x1000>, > + <0x0 0xff3b1000 0x0 0x1000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, > + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; > + clock-names = "clk_ref", "clk_phy"; > + freq-table-hz = <0 0>, <0 0>; > + /* offset: 0x84; bit: 12 */ > + /* offset: 0x84; bit: 7 */ > + resets = <&crg_rst 0x84 12>, > + <&crg_rst 0x84 7>; > + reset-names = "rst", "assert"; > + }; > + > + &ufs { > + reset-gpio = <&gpio18 1 0>; > + status = "okay"; Don't show status or the chip/board split in examples. > + }; > + > -- > 2.11.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 3/5] arm64: dts: add ufs dts node 2017-10-13 7:49 [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC Li Wei 2017-10-13 7:49 ` [PATCH v4 1/5] scsi: ufs: add Hisilicon ufs driver code Li Wei 2017-10-13 7:49 ` [PATCH v4 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs Li Wei @ 2017-10-13 7:49 ` Li Wei 2017-10-13 7:49 ` [PATCH v4 4/5] arm64: defconfig: enable configs for Hisilicon ufs Li Wei 2017-10-13 7:49 ` [PATCH v4 5/5] arm64: defconfig: enable f2fs and squashfs Li Wei 4 siblings, 0 replies; 9+ messages in thread From: Li Wei @ 2017-10-13 7:49 UTC (permalink / raw) To: robh+dt, mark.rutland, xuwei5, catalin.marinas, will.deacon, vinholikatti, jejb, martin.petersen, khilman, arnd, gregory.clement, thomas.petazzoni, yamada.masahiro, riku.voipio, treding, krzk, eric, devicetree, linux-kernel, linux-arm-kernel, linux-scsi Cc: guodong.xu, liwei213, fengbaopeng, lihuan41, wangyupeng4 arm64: dts: add ufs node for Hisilicon. Signed-off-by: Li Wei <liwei213@huawei.com> --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 5 +++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 19 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index fd4705c451e2..457645a2b53f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -276,3 +276,8 @@ interrupts = <3 IRQ_TYPE_EDGE_RISING>; }; }; + +&ufs { + reset-gpio = <&gpio18 1 0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index b7a90d632959..a24ab8472347 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -978,5 +978,24 @@ clocks = <&crg_ctrl HI3660_OSC32K>; clock-names = "apb_pclk"; }; + + ufs: ufs@ff3b0000 { + compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; + /* 0: HCI standard */ + /* 1: UFS SYS CTRL */ + reg = <0x0 0xff3b0000 0x0 0x1000>, + <0x0 0xff3b1000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; + clock-names = "clk_ref", "clk_phy"; + freq-table-hz = <0 0>, <0 0>; + /* offset: 0x84; bit: 12 */ + /* offset: 0x84; bit: 7 */ + resets = <&crg_rst 0x84 12>, + <&crg_rst 0x84 7>; + reset-names = "rst", "assert"; + }; }; }; -- 2.11.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 4/5] arm64: defconfig: enable configs for Hisilicon ufs 2017-10-13 7:49 [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC Li Wei ` (2 preceding siblings ...) 2017-10-13 7:49 ` [PATCH v4 3/5] arm64: dts: add ufs dts node Li Wei @ 2017-10-13 7:49 ` Li Wei 2017-10-13 7:49 ` [PATCH v4 5/5] arm64: defconfig: enable f2fs and squashfs Li Wei 4 siblings, 0 replies; 9+ messages in thread From: Li Wei @ 2017-10-13 7:49 UTC (permalink / raw) To: robh+dt, mark.rutland, xuwei5, catalin.marinas, will.deacon, vinholikatti, jejb, martin.petersen, khilman, arnd, gregory.clement, thomas.petazzoni, yamada.masahiro, riku.voipio, treding, krzk, eric, devicetree, linux-kernel, linux-arm-kernel, linux-scsi Cc: guodong.xu, liwei213, fengbaopeng, lihuan41, wangyupeng4 This enable configs for Hisilicon Hixxxx UFS driver. Signed-off-by: Li Wei <liwei213@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 34480e9af2e7..8aff981915f5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -168,6 +168,9 @@ CONFIG_BLK_DEV_SD=y CONFIG_SCSI_SAS_ATA=y CONFIG_SCSI_HISI_SAS=y CONFIG_SCSI_HISI_SAS_PCI=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_HISI=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y -- 2.11.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 5/5] arm64: defconfig: enable f2fs and squashfs 2017-10-13 7:49 [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC Li Wei ` (3 preceding siblings ...) 2017-10-13 7:49 ` [PATCH v4 4/5] arm64: defconfig: enable configs for Hisilicon ufs Li Wei @ 2017-10-13 7:49 ` Li Wei 4 siblings, 0 replies; 9+ messages in thread From: Li Wei @ 2017-10-13 7:49 UTC (permalink / raw) To: robh+dt, mark.rutland, xuwei5, catalin.marinas, will.deacon, vinholikatti, jejb, martin.petersen, khilman, arnd, gregory.clement, thomas.petazzoni, yamada.masahiro, riku.voipio, treding, krzk, eric, devicetree, linux-kernel, linux-arm-kernel, linux-scsi Cc: guodong.xu, liwei213, fengbaopeng, lihuan41, wangyupeng4 Partitions in HiKey960 are formatted as f2fs and squashfs. f2fs is for userdata; squashfs is for system. Both partitions are required by Android. Signed-off-by: Li Wei <liwei213@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> --- arch/arm64/configs/defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8aff981915f5..0a8a843cd0be 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -555,6 +555,7 @@ CONFIG_ACPI_APEI_GHES=y CONFIG_ACPI_APEI_PCIEAER=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y +CONFIG_F2FS_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y @@ -570,6 +571,13 @@ CONFIG_HUGETLBFS=y CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=y CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y CONFIG_NFS_FS=y CONFIG_NFS_V4=y CONFIG_NFS_V4_1=y -- 2.11.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC @ 2017-10-20 8:50 Li Wei 2017-10-20 8:50 ` [PATCH v4 1/5] scsi: ufs: add Hisilicon ufs driver code Li Wei 0 siblings, 1 reply; 9+ messages in thread From: Li Wei @ 2017-10-20 8:50 UTC (permalink / raw) To: robh+dt, mark.rutland, xuwei5, catalin.marinas, will.deacon, vinholikatti, jejb, martin.petersen, khilman, arnd, gregory.clement, thomas.petazzoni, yamada.masahiro, riku.voipio, treding, krzk, eric, devicetree, linux-kernel, linux-arm-kernel, linux-scsi Cc: guodong.xu, liwei213, fengbaopeng, lihuan41, wangyupeng4 This patchset adds driver support for UFS for Hi3660 SoC. It is verified on HiKey960 board. Li Wei (5): scsi: ufs: add Hisilicon ufs driver code dt-bindings: scsi: ufs: add document for hisi-ufs arm64: dts: add ufs dts node arm64: defconfig: enable configs for Hisilicon ufs arm64: defconfig: enable f2fs and squashfs Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 47 ++ arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 5 + arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 19 + arch/arm64/configs/defconfig | 11 + drivers/scsi/ufs/Kconfig | 9 + drivers/scsi/ufs/Makefile | 1 + drivers/scsi/ufs/ufs-hisi.c | 625 +++++++++++++++++++++ drivers/scsi/ufs/ufs-hisi.h | 161 ++++++ 8 files changed, 878 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt create mode 100644 drivers/scsi/ufs/ufs-hisi.c create mode 100644 drivers/scsi/ufs/ufs-hisi.h -- 2.11.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 1/5] scsi: ufs: add Hisilicon ufs driver code 2017-10-20 8:50 [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC Li Wei @ 2017-10-20 8:50 ` Li Wei 0 siblings, 0 replies; 9+ messages in thread From: Li Wei @ 2017-10-20 8:50 UTC (permalink / raw) To: robh+dt, mark.rutland, xuwei5, catalin.marinas, will.deacon, vinholikatti, jejb, martin.petersen, khilman, arnd, gregory.clement, thomas.petazzoni, yamada.masahiro, riku.voipio, treding, krzk, eric, devicetree, linux-kernel, linux-arm-kernel, linux-scsi Cc: guodong.xu, liwei213, fengbaopeng, lihuan41, wangyupeng4 add Hisilicon ufs driver code. Signed-off-by: Li Wei <liwei213@huawei.com> Signed-off-by: Geng Jianfeng <gengjianfeng@hisilicon.com> Signed-off-by: Zang Leigang <zangleigang@hisilicon.com> Signed-off-by: Yu Jianfeng <steven.yujianfeng@hisilicon.com> --- drivers/scsi/ufs/Kconfig | 9 + drivers/scsi/ufs/Makefile | 1 + drivers/scsi/ufs/ufs-hisi.c | 625 ++++++++++++++++++++++++++++++++++++++++++++ drivers/scsi/ufs/ufs-hisi.h | 161 ++++++++++++ 4 files changed, 796 insertions(+) create mode 100644 drivers/scsi/ufs/ufs-hisi.c create mode 100644 drivers/scsi/ufs/ufs-hisi.h diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig index e27b4d4e6ae2..bf2ff5628b15 100644 --- a/drivers/scsi/ufs/Kconfig +++ b/drivers/scsi/ufs/Kconfig @@ -80,6 +80,15 @@ config SCSI_UFSHCD_PLATFORM If unsure, say N. +config SCSI_UFS_HISI + tristate "Hisilicon specific hooks to UFS controller platform driver" + depends on (ARCH_HISI || COMPILE_TEST) && SCSI_UFSHCD_PLATFORM + ---help--- + This selects the Hisilicon specific additions to UFSHCD platform driver. + + Select this if you have UFS controller on Hisilicon chipset. + If unsure, say N. + config SCSI_UFS_DWC_TC_PLATFORM tristate "DesignWare platform support using a G210 Test Chip" depends on SCSI_UFSHCD_PLATFORM diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile index 6e77cb0bfee9..9f2c17029a38 100644 --- a/drivers/scsi/ufs/Makefile +++ b/drivers/scsi/ufs/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o +obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c new file mode 100644 index 000000000000..8b7aea2d44c5 --- /dev/null +++ b/drivers/scsi/ufs/ufs-hisi.c @@ -0,0 +1,625 @@ +/* + * + * HiSilicon Hixxxx UFS Driver + * + * Copyright (c) 2016-2017 Linaro Ltd. + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/gpio.h> +#include <linux/time.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_gpio.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include "ufshcd.h" +#include "ufshcd-pltfrm.h" +#include "unipro.h" +#include "ufs-hisi.h" +#include "ufshci.h" + +static int ufs_hisi_check_hibern8(struct ufs_hba *hba) +{ + int err; + u32 tx_fsm_val_0; + u32 tx_fsm_val_1; + unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); + + do { + err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), + &tx_fsm_val_0); + err |= ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); + if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 && + tx_fsm_val_1 == TX_FSM_HIBERN8)) + break; + + /* sleep for max. 200us */ + usleep_range(100, 200); + } while (time_before(jiffies, timeout)); + + /* + * we might have scheduled out for long during polling so + * check the state again. + */ + if (time_after(jiffies, timeout)) { + err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), + &tx_fsm_val_0); + err |= ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); + } + + if (err) { + dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", + __func__, err); + } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 || + tx_fsm_val_1 != TX_FSM_HIBERN8) { + err = -1; + dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", + __func__, tx_fsm_val_0, tx_fsm_val_1); + } + + return err; +} + +static void ufs_hisi_clk_init(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN) + mdelay(1); + /* use abb clk */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL); + ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN); + /* open mphy ref clk */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); +} + +static void ufs_hisi_soc_init(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + u32 reg; + + if (!IS_ERR(host->rst)) + reset_control_assert(host->rst); + + /* HC_PSW powerup */ + ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL); + udelay(10); + /* notify PWR ready */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL); + ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0, + UFS_DEVICE_RESET_CTRL); + + if (gpio_is_valid(host->reset_gpio)) + gpio_direction_output(host->reset_gpio, 0); + + reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL); + reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK; + /* set cfg clk freq */ + ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL); + /* set ref clk freq */ + ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL); + /* bypass ufs clk gate */ + ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS, + CLOCK_GATE_BYPASS); + ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL); + + /* open psw clk */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL); + /* disable ufshc iso */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL); + /* disable phy iso */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN); + /* notice iso disable */ + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL); + + if (!IS_ERR(host->assert)) + reset_control_deassert(host->assert); + + /* disable lp_reset_n */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN); + mdelay(1); + + if (gpio_is_valid(host->reset_gpio)) + gpio_direction_output(host->reset_gpio, 1); + + ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET, + UFS_DEVICE_RESET_CTRL); + + msleep(20); + + /* + * enable the fix of linereset recovery, + * and enable rx_reset/tx_rest beat + * enable ref_clk_en override(bit5) & + * override value = 1(bit4), with mask + */ + ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL); + + if (!IS_ERR(host->rst)) + reset_control_deassert(host->rst); +} + +static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba) +{ + int err; + uint32_t value; + uint32_t reg; + + /* Unipro VS_mphy_disable */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1); + /* PA_HSSeries */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2); + /* MPHY CBRATESEL */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1); + /* MPHY CBOVRCTRL2 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D); + /* MPHY CBOVRCTRL3 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); + /* Unipro VS_MphyCfgUpdt */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + /* MPHY RXOVRCTRL4 rx0 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58); + /* MPHY RXOVRCTRL4 rx1 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58); + /* MPHY RXOVRCTRL5 rx0 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB); + /* MPHY RXOVRCTRL5 rx1 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB); + /* MPHY RXSQCONTROL rx0 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1); + /* MPHY RXSQCONTROL rx1 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1); + /* Unipro VS_MphyCfgUpdt */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + /* Gear3 Synclength */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4A); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4A); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4A); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4A); + /* Tactive RX */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7); + /* Thibernate Tx */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5); + + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + /* Unipro VS_mphy_disable */ + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value); + if (value != 0x1) + dev_info(hba->dev, + "Warring!!! Unipro VS_mphy_disable is 0x%x\n", value); + + /* Unipro VS_mphy_disable */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0); + err = ufs_hisi_check_hibern8(hba); + if (err) + dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n"); + + ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV); + + /* disable auto H8 */ + reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); + reg = reg & (~UFS_AHIT_AH8ITV_MASK); + ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); + + /* Unipro PA_Local_TX_LCC_Enable */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x155E, 0x0), 0x0); + /* close Unipro VS_Mk2ExtnSupport */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0); + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value); + if (value != 0) { + /* Ensure close success */ + dev_info(hba->dev, "WARN: close VS_Mk2ExtnSupport failed\n"); + } + + return err; +} + +static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + /* Unipro DL_AFC0CreditThreshold */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0); + /* Unipro DL_TC0OutAckThreshold */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0); + /* Unipro DL_TC0TXFCThreshold */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9); + + /* not bypass ufs clk gate */ + ufs_sys_ctrl_clr_bits(host, MASK_UFS_CLK_GATE_BYPASS, + CLOCK_GATE_BYPASS); + ufs_sys_ctrl_clr_bits(host, MASK_UFS_SYSCRTL_BYPASS, + UFS_SYSCTRL); + + return 0; +} + +static int ufs_hisi_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + int err = 0; + + switch (status) { + case PRE_CHANGE: + err = ufs_hisi_link_startup_pre_change(hba); + break; + case POST_CHANGE: + err = ufs_hisi_link_startup_post_change(hba); + break; + default: + break; + } + + return err; +} + +struct ufs_hisi_dev_params { + u32 pwm_rx_gear; /* pwm rx gear to work in */ + u32 pwm_tx_gear; /* pwm tx gear to work in */ + u32 hs_rx_gear; /* hs rx gear to work in */ + u32 hs_tx_gear; /* hs tx gear to work in */ + u32 rx_lanes; /* number of rx lanes */ + u32 tx_lanes; /* number of tx lanes */ + u32 rx_pwr_pwm; /* rx pwm working pwr */ + u32 tx_pwr_pwm; /* tx pwm working pwr */ + u32 rx_pwr_hs; /* rx hs working pwr */ + u32 tx_pwr_hs; /* tx hs working pwr */ + u32 hs_rate; /* rate A/B to work in HS */ + u32 desired_working_mode; +}; + +static int ufs_hisi_get_pwr_dev_param( + struct ufs_hisi_dev_params *hisi_param, + struct ufs_pa_layer_attr *dev_max, + struct ufs_pa_layer_attr *agreed_pwr) +{ + int min_hisi_gear; + int min_dev_gear; + bool is_dev_sup_hs = false; + bool is_hisi_max_hs = false; + + if (dev_max->pwr_rx == FASTAUTO_MODE || dev_max->pwr_rx == FAST_MODE) + is_dev_sup_hs = true; + + if (hisi_param->desired_working_mode == FAST) { + is_hisi_max_hs = true; + min_hisi_gear = min_t(u32, hisi_param->hs_rx_gear, + hisi_param->hs_tx_gear); + } else { + min_hisi_gear = min_t(u32, hisi_param->pwm_rx_gear, + hisi_param->pwm_tx_gear); + } + + /* + * device doesn't support HS but + * hisi_param->desired_working_mode is HS, + * thus device and hisi_param don't agree + */ + if (!is_dev_sup_hs && is_hisi_max_hs) { + pr_err("%s: device not support HS\n", __func__); + return -ENOTSUPP; + } else if (is_dev_sup_hs && is_hisi_max_hs) { + /* + * since device supports HS, it supports FAST_MODE. + * since hisi_param->desired_working_mode is also HS + * then final decision (FAST/FASTAUTO) is done according + * to hisi_params as it is the restricting factor + */ + agreed_pwr->pwr_rx = agreed_pwr->pwr_tx = + hisi_param->rx_pwr_hs; + } else { + /* + * here hisi_param->desired_working_mode is PWM. + * it doesn't matter whether device supports HS or PWM, + * in both cases hisi_param->desired_working_mode will + * determine the mode + */ + agreed_pwr->pwr_rx = agreed_pwr->pwr_tx = + hisi_param->rx_pwr_pwm; + } + + /* + * we would like tx to work in the minimum number of lanes + * between device capability and vendor preferences. + * the same decision will be made for rx + */ + agreed_pwr->lane_tx = + min_t(u32, dev_max->lane_tx, hisi_param->tx_lanes); + agreed_pwr->lane_rx = + min_t(u32, dev_max->lane_rx, hisi_param->rx_lanes); + + /* device maximum gear is the minimum between device rx and tx gears */ + min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx); + + /* + * if both device capabilities and vendor pre-defined preferences are + * both HS or both PWM then set the minimum gear to be the chosen + * working gear. + * if one is PWM and one is HS then the one that is PWM get to decide + * what is the gear, as it is the one that also decided previously what + * pwr the device will be configured to. + */ + if ((is_dev_sup_hs && is_hisi_max_hs) || + (!is_dev_sup_hs && !is_hisi_max_hs)) + agreed_pwr->gear_rx = agreed_pwr->gear_tx = + min_t(u32, min_dev_gear, min_hisi_gear); + else + agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_hisi_gear; + + agreed_pwr->hs_rate = hisi_param->hs_rate; + + pr_info("ufs final power mode: gear = %d, lane = %d, pwr = %d, rate = %d\n", + agreed_pwr->gear_rx, agreed_pwr->lane_rx, agreed_pwr->pwr_rx, + agreed_pwr->hs_rate); + return 0; +} + +static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba) +{ + /* update */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1); + /* PA_TxSkip */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0); + /*PA_PWRModeUserData0 = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191); + /*PA_PWRModeUserData1 = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535); + /*PA_PWRModeUserData2 = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767); + /*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191); + /*DME_TC0ReplayTimeOutVal = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535); + /*DME_AFC0ReqTimeOutVal = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767); + /*PA_PWRModeUserData3 = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191); + /*PA_PWRModeUserData4 = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535); + /*PA_PWRModeUserData5 = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767); + /*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191); + /*DME_TC1ReplayTimeOutVal = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535); + /*DME_AFC1ReqTimeOutVal = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767); +} + +static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, + struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) +{ + struct ufs_hisi_dev_params ufs_hisi_cap; + int ret = 0; + uint32_t value; + + if (!dev_req_params) { + dev_err(hba->dev, + "%s: incoming dev_req_params is NULL\n", __func__); + ret = -EINVAL; + goto out; + } + + switch (status) { + case PRE_CHANGE: + ufs_hisi_cap.rx_lanes = UFS_HISI_LIMIT_NUM_LANES_RX; + ufs_hisi_cap.tx_lanes = UFS_HISI_LIMIT_NUM_LANES_TX; + ufs_hisi_cap.hs_rx_gear = UFS_HISI_LIMIT_HSGEAR_RX; + ufs_hisi_cap.hs_tx_gear = UFS_HISI_LIMIT_HSGEAR_TX; + ufs_hisi_cap.pwm_rx_gear = UFS_HISI_LIMIT_PWMGEAR_RX; + ufs_hisi_cap.pwm_tx_gear = UFS_HISI_LIMIT_PWMGEAR_TX; + ufs_hisi_cap.rx_pwr_pwm = UFS_HISI_LIMIT_RX_PWR_PWM; + ufs_hisi_cap.tx_pwr_pwm = UFS_HISI_LIMIT_TX_PWR_PWM; + ufs_hisi_cap.rx_pwr_hs = UFS_HISI_LIMIT_RX_PWR_HS; + ufs_hisi_cap.tx_pwr_hs = UFS_HISI_LIMIT_TX_PWR_HS; + ufs_hisi_cap.hs_rate = UFS_HISI_LIMIT_HS_RATE; + ufs_hisi_cap.desired_working_mode = UFS_HISI_LIMIT_DESIRED_MODE; + + ret = ufs_hisi_get_pwr_dev_param( + &ufs_hisi_cap, dev_max_params, dev_req_params); + if (ret) { + dev_err(hba->dev, + "%s: failed to determine capabilities\n", __func__); + goto out; + } + + dev_info(hba->dev, "set TX_EQUALIZER 3.5db\n"); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0037, 0x0), 0x1); + if ((dev_req_params->lane_tx > 1) && + (dev_req_params->lane_rx > 1)) + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0037, 0x1), 0x1); + + ufs_hisi_pwr_change_pre_change(hba); + break; + case POST_CHANGE: + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x0037, 0x0), &value); + dev_info(hba->dev, + "check TX_EQUALIZER DB value lane0 = 0x%x\n", value); + if ((dev_req_params->lane_tx > 1) && + (dev_req_params->lane_rx > 1)) { + ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(0x0037, 0x1), &value); + dev_info(hba->dev, + "TX_EQUALIZER DB value lane1 = 0x%x\n", value); + } + break; + default: + ret = -EINVAL; + break; + } +out: + return ret; +} + +static int ufs_hisi_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + if (ufshcd_is_runtime_pm(pm_op)) + return 0; + + if (host->in_suspend) { + WARN_ON(1); + return 0; + } + + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + udelay(10); + /* set ref_dig_clk override of PHY PCS to 0 */ + ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL); + + host->in_suspend = true; + + return 0; +} + +static int ufs_hisi_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + if (!host->in_suspend) + return 0; + + /* set ref_dig_clk override of PHY PCS to 1 */ + ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL); + udelay(10); + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + + host->in_suspend = false; + return 0; +} + +static int ufs_hisi_get_resource(struct ufs_hisi_host *host) +{ + struct resource *mem_res; + struct device *dev = host->hba->dev; + struct platform_device *pdev = to_platform_device(dev); + + /* get resource of ufs sys ctrl */ + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + host->ufs_sys_ctrl = devm_ioremap_resource(dev, mem_res); + + if (IS_ERR(host->ufs_sys_ctrl)) + return PTR_ERR(host->ufs_sys_ctrl); + + host->rst = devm_reset_control_get(dev, "rst"); + host->assert = devm_reset_control_get(dev, "assert"); + + return 0; +} + +static void ufs_hisi_set_pm_lvl(struct ufs_hba *hba) +{ + hba->rpm_lvl = UFS_PM_LVL_1; + hba->spm_lvl = UFS_PM_LVL_3; +} + +/** + * ufs_hisi_init + * @hba: host controller instance + */ +static int ufs_hisi_init(struct ufs_hba *hba) +{ + int err; + struct device *dev = hba->dev; + struct ufs_hisi_host *host; + + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); + if (!host) + return -ENOMEM; + + host->hba = hba; + ufshcd_set_variant(hba, host); + + host->reset_gpio = of_get_named_gpio(hba->dev->of_node, + "reset-gpio", 0); + if (gpio_is_valid(host->reset_gpio)) { + err = devm_gpio_request_one(dev, host->reset_gpio, + GPIOF_DIR_OUT, "hisi_ufs_reset"); + if (err) + dev_err(dev, "could not acquire gpio (err=%d)\n", err); + } + + ufs_hisi_set_pm_lvl(hba); + + err = ufs_hisi_get_resource(host); + if (err) { + ufshcd_set_variant(hba, NULL); + return err; + } + + ufs_hisi_clk_init(hba); + + ufs_hisi_soc_init(hba); + + return 0; +} + +static struct ufs_hba_variant_ops ufs_hba_hisi_vops = { + .name = "hisi", + .init = ufs_hisi_init, + .link_startup_notify = ufs_hisi_link_startup_notify, + .pwr_change_notify = ufs_hisi_pwr_change_notify, + .suspend = ufs_hisi_suspend, + .resume = ufs_hisi_resume, +}; + +static int ufs_hisi_probe(struct platform_device *pdev) +{ + return ufshcd_pltfrm_init(pdev, &ufs_hba_hisi_vops); +} + +static int ufs_hisi_remove(struct platform_device *pdev) +{ + struct ufs_hba *hba = platform_get_drvdata(pdev); + + ufshcd_remove(hba); + return 0; +} + +static const struct of_device_id ufs_hisi_of_match[] = { + { .compatible = "hisilicon,hi3660-ufs" }, + {}, +}; + +static const struct dev_pm_ops ufs_hisi_pm_ops = { + .suspend = ufshcd_pltfrm_suspend, + .resume = ufshcd_pltfrm_resume, + .runtime_suspend = ufshcd_pltfrm_runtime_suspend, + .runtime_resume = ufshcd_pltfrm_runtime_resume, + .runtime_idle = ufshcd_pltfrm_runtime_idle, +}; + +static struct platform_driver ufs_hisi_pltform = { + .probe = ufs_hisi_probe, + .remove = ufs_hisi_remove, + .shutdown = ufshcd_pltfrm_shutdown, + .driver = { + .name = "ufshcd-hisi", + .pm = &ufs_hisi_pm_ops, + .of_match_table = of_match_ptr(ufs_hisi_of_match), + }, +}; +module_platform_driver(ufs_hisi_pltform); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:ufshcd-hisi"); +MODULE_DESCRIPTION("HiSilicon Hixxxx UFS Driver"); diff --git a/drivers/scsi/ufs/ufs-hisi.h b/drivers/scsi/ufs/ufs-hisi.h new file mode 100644 index 000000000000..c2cf5830d26c --- /dev/null +++ b/drivers/scsi/ufs/ufs-hisi.h @@ -0,0 +1,161 @@ +/* Copyright (c) 2017, HiSilicon. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef UFS_HISI_H_ +#define UFS_HISI_H_ + +#define HBRN8_POLL_TOUT_MS 1000 + +/* + * pericrg specific define + */ +#define PEREN5_OFFSET (0x050) +#define PERRSTEN3_OFFSET (0x084) +#define PERRSTDIS3_OFFSET (0x088) +#define PERRSTSTAT3_OFFSET (0x08C) +#define CLKDIV16_OFFSET (0x0E8) +#define CLKDIV17_OFFSET (0x0EC) +#define CLKDIV21_OFFSET (0x0FC) +#define UFS_ARESET UFS_BIT(7) +#define RST_UFS UFS_BIT(12) + +/* + * ufs sysctrl specific define + */ +#define PSW_POWER_CTRL (0x04) +#define PHY_ISO_EN (0x08) +#define HC_LP_CTRL (0x0C) +#define PHY_CLK_CTRL (0x10) +#define PSW_CLK_CTRL (0x14) +#define CLOCK_GATE_BYPASS (0x18) +#define RESET_CTRL_EN (0x1C) +#define PHY_RESET_STATUS (0x28) +#define UFS_SYSCTRL (0x5C) +#define UFS_DEVICE_RESET_CTRL (0x60) +#define UFS_APB_ADDR_MASK (0x64) + +#define BIT_UFS_PSW_ISO_CTRL (1 << 16) +#define BIT_UFS_PSW_MTCMOS_EN (1 << 0) +#define BIT_UFS_REFCLK_ISO_EN (1 << 16) +#define BIT_UFS_PHY_ISO_CTRL (1 << 0) +#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) +#define BIT_SYSCTRL_LP_PWR_GATE (1 << 0) +#define BIT_SYSCTRL_PWR_READY (1 << 8) +#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) +#define MASK_SYSCTRL_REF_CLOCK_SEL (0x3 << 8) +#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) +#define UFS_FREQ_CFG_CLK (0x39) +#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) +#define MASK_UFS_CLK_GATE_BYPASS (0x3F) +#define BIT_STATUS_LP_RESETCOMPLETE (1 << 0) +#define BIT_SYSCTRL_LP_RESET_N (1 << 0) +#define BIT_UFS_REFCLK_SRC_SEl (1 << 0) +#define MASK_UFS_SYSCRTL_BYPASS (0x3F << 16) +#define MASK_UFS_DEVICE_RESET (0x1 << 16) +#define BIT_UFS_DEVICE_RESET (0x1) + +/* + * M-TX Configuration Attributes for Hixxxx + */ +#define MPHY_TX_FSM_STATE 0x41 +#define TX_FSM_DISABLED 0x0 +#define TX_FSM_HIBERN8 0x1 +#define TX_FSM_SLEEP 0x2 +#define TX_FSM_STALL 0x3 +#define TX_FSM_LS_BURST 0x4 +#define TX_FSM_HS_BURST 0x5 +#define TX_FSM_LINE_CFG 0x6 +#define TX_FSM_LINE_RESET 0x7 + +/* + * Hixxxx UFS HC specific Registers + */ +enum { + UFS_REG_OCPTHRTL = 0xc0, + UFS_REG_OOCPR = 0xc4, + + UFS_REG_CDACFG = 0xd0, + UFS_REG_CDATX1 = 0xd4, + UFS_REG_CDATX2 = 0xd8, + UFS_REG_CDARX1 = 0xdc, + UFS_REG_CDARX2 = 0xe0, + UFS_REG_CDASTA = 0xe4, + + UFS_REG_LBMCFG = 0xf0, + UFS_REG_LBMSTA = 0xf4, + UFS_REG_UFSMODE = 0xf8, + + UFS_REG_HCLKDIV = 0xfc, +}; + +/* AHIT - Auto-Hibernate Idle Timer */ +#define UFS_AHIT_AH8ITV_MASK 0x3FF + +#define UFS_AHIT_AUTOH8_TIMER (0x1001) + +/* REG UFS_REG_OCPTHRTL definition */ +#define LP_PGE UFS_BIT(16) +#define LP_AH8_PGE UFS_BIT(17) + +#define UFS_HCLKDIV_NORMAL_VALUE 0xE4 +#define UFS_HCLKDIV_FPGA_VALUE 0x28 + +/* Hixxxx UFS Unipro specific Registers */ +#define VS_ULPH8_Cntrl 0xd0af +#define Ulp_Ulp_CtrlMode UFS_BIT(3) + +/* vendor specific pre-defined parameters */ +#define SLOW 1 +#define FAST 2 + +#define UFS_HISI_LIMIT_NUM_LANES_RX 2 +#define UFS_HISI_LIMIT_NUM_LANES_TX 2 +#define UFS_HISI_LIMIT_HSGEAR_RX UFS_HS_G3 +#define UFS_HISI_LIMIT_HSGEAR_TX UFS_HS_G3 +#define UFS_HISI_LIMIT_PWMGEAR_RX UFS_PWM_G1 +#define UFS_HISI_LIMIT_PWMGEAR_TX UFS_PWM_G1 +#define UFS_HISI_LIMIT_RX_PWR_PWM SLOWAUTO_MODE +#define UFS_HISI_LIMIT_TX_PWR_PWM SLOWAUTO_MODE +#define UFS_HISI_LIMIT_RX_PWR_HS FAST_MODE +#define UFS_HISI_LIMIT_TX_PWR_HS FAST_MODE +#define UFS_HISI_LIMIT_HS_RATE PA_HS_MODE_B +#define UFS_HISI_LIMIT_DESIRED_MODE FAST + +struct ufs_hisi_host { + struct ufs_hba *hba; + void __iomem *ufs_sys_ctrl; + struct reset_control *rst; + struct reset_control *assert; + + int avail_ln_rx; + int avail_ln_tx; + + u32 busthrtl_backup; + u32 reset_gpio; + + bool in_suspend; + + struct ufs_pa_layer_attr dev_req_params; +}; + +#define ufs_sys_ctrl_writel(host, val, reg) \ + writel((val), (host)->ufs_sys_ctrl + (reg)) +#define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg)) +#define ufs_sys_ctrl_set_bits(host, mask, reg) \ + ufs_sys_ctrl_writel( \ + (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg)) +#define ufs_sys_ctrl_clr_bits(host, mask, reg) \ + ufs_sys_ctrl_writel((host), \ + ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \ + (reg)) +#endif /* UFS_HISI_H_ */ -- 2.11.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-10-20 8:50 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2017-10-13 7:49 [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC Li Wei
2017-10-13 7:49 ` [PATCH v4 1/5] scsi: ufs: add Hisilicon ufs driver code Li Wei
2017-10-13 7:49 ` [PATCH v4 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs Li Wei
[not found] ` <20171013074936.97284-3-liwei213-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2017-10-17 21:17 ` Rob Herring
2017-10-18 10:23 ` 答复: " liwei (CM)
2017-10-13 7:49 ` [PATCH v4 3/5] arm64: dts: add ufs dts node Li Wei
2017-10-13 7:49 ` [PATCH v4 4/5] arm64: defconfig: enable configs for Hisilicon ufs Li Wei
2017-10-13 7:49 ` [PATCH v4 5/5] arm64: defconfig: enable f2fs and squashfs Li Wei
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2017-10-20 8:50 [PATCH v4 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC Li Wei
2017-10-20 8:50 ` [PATCH v4 1/5] scsi: ufs: add Hisilicon ufs driver code Li Wei
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