[PATCH 0/9] drm/panel: simple: improve definition of display modes and add more panels

[PATCH 0/9] drm/panel: simple: improve definition of display modes and add more panels

[Lothar Waßmann]

The first two patches of this patchset simplify the definition of
display modes in the driver and make it less error prone.

Patch 3 & 4 add support for overriding certain settings defined in the
panel definitions via DT entries to match up HW interfacing variants.

The remaining patches add support for various panels that may be used
with the Ka-Ro electronics TX module series.

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[PATCH 1/9] drm/panel: simple: add a macro for defining display modes in a simpler and less error prone way

[Lothar Waßmann]

Create a macro that eases the definition of display mode parameters by
accecpting the parameters:
freq, hactive, hfront-porch, hsynclen, hback-porch,
vactive, vfront-porch, vsynclen, vback-porch, vrefresh
that can be usually directly taken from an LCD datasheet.

Put the calculations that are now open coded repeating the same
parameters multiple times into the macro expansion.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
---
 drivers/gpu/drm/panel/panel-simple.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 474fa75..dec639d 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -411,6 +411,20 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 };
 
+#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
+	.clock = freq,							\
+	.hdisplay = ha,							\
+	.hsync_start = (ha) + (hfp),					\
+	.hsync_end = (ha) + (hfp) + (hs),				\
+	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
+	.vdisplay = (va),						\
+	.vsync_start = (va) + (vfp),					\
+	.vsync_end = (va) + (vfp) + (vs),				\
+	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
+	.vrefresh = vr,							\
+	.flags = flgs,							\
+	}
+
 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 	.clock = 33333,
 	.hdisplay = 800,
-- 
2.1.4

[PATCH 2/9] drm/panel: simple: simplify display_mode definitions by using macro

[Lothar Waßmann]

Use the newly defined macro to generate the display_mode data entries
for all panels. This reduces the code size significantly and makes the
code more readable.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
---
 drivers/gpu/drm/panel/panel-simple.c | 799 ++++++-----------------------------
 1 file changed, 134 insertions(+), 665 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index dec639d..fde9c41 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -89,6 +89,20 @@ struct panel_simple {
 	struct gpio_desc *enable_gpio;
 };
 
+#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
+	.clock = freq,							\
+	.hdisplay = ha,							\
+	.hsync_start = (ha) + (hfp),					\
+	.hsync_end = (ha) + (hfp) + (hs),				\
+	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
+	.vdisplay = (va),						\
+	.vsync_start = (va) + (vfp),					\
+	.vsync_end = (va) + (vfp) + (vs),				\
+	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
+	.vrefresh = vr,							\
+	.flags = flgs,							\
+}
+
 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 {
 	return container_of(panel, struct panel_simple, base);
@@ -386,19 +400,9 @@ static void panel_simple_shutdown(struct device *dev)
 	panel_simple_unprepare(&panel->base);
 }
 
-static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 2,
-	.hsync_end = 480 + 2 + 41,
-	.htotal = 480 + 2 + 41 + 2,
-	.vdisplay = 272,
-	.vsync_start = 272 + 2,
-	.vsync_end = 272 + 2 + 10,
-	.vtotal = 272 + 2 + 10 + 2,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
-};
+static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode =
+	SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 10, 2, 60,
+			DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 
 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
 	.modes = &ampire_am_480272h3tmqw_t01h_mode,
@@ -411,33 +415,9 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 };
 
-#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
-	.clock = freq,							\
-	.hdisplay = ha,							\
-	.hsync_start = (ha) + (hfp),					\
-	.hsync_end = (ha) + (hfp) + (hs),				\
-	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
-	.vdisplay = (va),						\
-	.vsync_start = (va) + (vfp),					\
-	.vsync_end = (va) + (vfp) + (vs),				\
-	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
-	.vrefresh = vr,							\
-	.flags = flgs,							\
-	}
-
-static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
-	.clock = 33333,
-	.hdisplay = 800,
-	.hsync_start = 800 + 0,
-	.hsync_end = 800 + 0 + 255,
-	.htotal = 800 + 0 + 255 + 0,
-	.vdisplay = 480,
-	.vsync_start = 480 + 2,
-	.vsync_end = 480 + 2 + 45,
-	.vtotal = 480 + 2 + 45 + 0,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
-};
+static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode =
+	SP_DISPLAY_MODE(33333, 800, 0, 255, 0, 480, 2, 45, 0, 60,
+			DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 
 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 	.modes = &ampire_am800480r3tmqwa1h_mode,
@@ -450,18 +430,8 @@ static const struct panel_desc ampire_am800480r3tmqwa1h = {
 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 };
 
-static const struct drm_display_mode auo_b101aw03_mode = {
-	.clock = 51450,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 156,
-	.hsync_end = 1024 + 156 + 8,
-	.htotal = 1024 + 156 + 8 + 156,
-	.vdisplay = 600,
-	.vsync_start = 600 + 16,
-	.vsync_end = 600 + 16 + 6,
-	.vtotal = 600 + 16 + 6 + 16,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode auo_b101aw03_mode =
+	SP_DISPLAY_MODE(51450, 1024, 156, 8, 156, 600, 16, 6, 16, 60, 0);
 
 static const struct panel_desc auo_b101aw03 = {
 	.modes = &auo_b101aw03_mode,
@@ -473,18 +443,8 @@ static const struct panel_desc auo_b101aw03 = {
 	},
 };
 
-static const struct drm_display_mode auo_b101ean01_mode = {
-	.clock = 72500,
-	.hdisplay = 1280,
-	.hsync_start = 1280 + 119,
-	.hsync_end = 1280 + 119 + 32,
-	.htotal = 1280 + 119 + 32 + 21,
-	.vdisplay = 800,
-	.vsync_start = 800 + 4,
-	.vsync_end = 800 + 4 + 20,
-	.vtotal = 800 + 4 + 20 + 8,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode auo_b101ean01_mode =
+	SP_DISPLAY_MODE(72500, 1280, 119, 32, 21, 800, 4, 20, 8, 60, 0);
 
 static const struct panel_desc auo_b101ean01 = {
 	.modes = &auo_b101ean01_mode,
@@ -496,19 +456,9 @@ static const struct panel_desc auo_b101ean01 = {
 	},
 };
 
-static const struct drm_display_mode auo_b101xtn01_mode = {
-	.clock = 72000,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 20,
-	.hsync_end = 1366 + 20 + 70,
-	.htotal = 1366 + 20 + 70,
-	.vdisplay = 768,
-	.vsync_start = 768 + 14,
-	.vsync_end = 768 + 14 + 42,
-	.vtotal = 768 + 14 + 42,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode auo_b101xtn01_mode =
+	SP_DISPLAY_MODE(72000, 1366, 20, 70, 0, 768, 14, 42, 0, 60,
+			DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 static const struct panel_desc auo_b101xtn01 = {
 	.modes = &auo_b101xtn01_mode,
@@ -520,18 +470,8 @@ static const struct panel_desc auo_b101xtn01 = {
 	},
 };
 
-static const struct drm_display_mode auo_b116xw03_mode = {
-	.clock = 70589,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 40,
-	.hsync_end = 1366 + 40 + 40,
-	.htotal = 1366 + 40 + 40 + 32,
-	.vdisplay = 768,
-	.vsync_start = 768 + 10,
-	.vsync_end = 768 + 10 + 12,
-	.vtotal = 768 + 10 + 12 + 6,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode auo_b116xw03_mode =
+	SP_DISPLAY_MODE(70589, 1366, 40, 40, 32, 768, 10, 12, 6, 60, 0);
 
 static const struct panel_desc auo_b116xw03 = {
 	.modes = &auo_b116xw03_mode,
@@ -543,18 +483,8 @@ static const struct panel_desc auo_b116xw03 = {
 	},
 };
 
-static const struct drm_display_mode auo_b133xtn01_mode = {
-	.clock = 69500,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 48,
-	.hsync_end = 1366 + 48 + 32,
-	.htotal = 1366 + 48 + 32 + 20,
-	.vdisplay = 768,
-	.vsync_start = 768 + 3,
-	.vsync_end = 768 + 3 + 6,
-	.vtotal = 768 + 3 + 6 + 13,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode auo_b133xtn01_mode =
+	SP_DISPLAY_MODE(69500, 1366, 48, 32, 20, 768, 3, 6, 13, 60, 0);
 
 static const struct panel_desc auo_b133xtn01 = {
 	.modes = &auo_b133xtn01_mode,
@@ -566,18 +496,8 @@ static const struct panel_desc auo_b133xtn01 = {
 	},
 };
 
-static const struct drm_display_mode auo_b133htn01_mode = {
-	.clock = 150660,
-	.hdisplay = 1920,
-	.hsync_start = 1920 + 172,
-	.hsync_end = 1920 + 172 + 80,
-	.htotal = 1920 + 172 + 80 + 60,
-	.vdisplay = 1080,
-	.vsync_start = 1080 + 25,
-	.vsync_end = 1080 + 25 + 10,
-	.vtotal = 1080 + 25 + 10 + 10,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode auo_b133htn01_mode =
+	SP_DISPLAY_MODE(150660, 1920, 172, 80, 60, 1080, 25, 10, 10, 60, 0);
 
 static const struct panel_desc auo_b133htn01 = {
 	.modes = &auo_b133htn01_mode,
@@ -680,18 +600,8 @@ static const struct panel_desc auo_p320hvn03 = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 };
 
-static const struct drm_display_mode auo_t215hvn01_mode = {
-	.clock = 148800,
-	.hdisplay = 1920,
-	.hsync_start = 1920 + 88,
-	.hsync_end = 1920 + 88 + 44,
-	.htotal = 1920 + 88 + 44 + 148,
-	.vdisplay = 1080,
-	.vsync_start = 1080 + 4,
-	.vsync_end = 1080 + 4 + 5,
-	.vtotal = 1080 + 4 + 5 + 36,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode auo_t215hvn01_mode =
+	SP_DISPLAY_MODE(148800, 1920, 88, 44, 148, 1080, 4, 5, 36, 60, 0);
 
 static const struct panel_desc auo_t215hvn01 = {
 	.modes = &auo_t215hvn01_mode,
@@ -707,18 +617,8 @@ static const struct panel_desc auo_t215hvn01 = {
 	}
 };
 
-static const struct drm_display_mode avic_tm070ddh03_mode = {
-	.clock = 51200,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 160,
-	.hsync_end = 1024 + 160 + 4,
-	.htotal = 1024 + 160 + 4 + 156,
-	.vdisplay = 600,
-	.vsync_start = 600 + 17,
-	.vsync_end = 600 + 17 + 1,
-	.vtotal = 600 + 17 + 1 + 17,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode avic_tm070ddh03_mode =
+	SP_DISPLAY_MODE(51200, 1024, 160, 4, 156, 600, 17, 1, 17, 60, 0);
 
 static const struct panel_desc avic_tm070ddh03 = {
 	.modes = &avic_tm070ddh03_mode,
@@ -736,30 +636,8 @@ static const struct panel_desc avic_tm070ddh03 = {
 };
 
 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
-	{
-		.clock = 71900,
-		.hdisplay = 1280,
-		.hsync_start = 1280 + 48,
-		.hsync_end = 1280 + 48 + 32,
-		.htotal = 1280 + 48 + 32 + 80,
-		.vdisplay = 800,
-		.vsync_start = 800 + 3,
-		.vsync_end = 800 + 3 + 5,
-		.vtotal = 800 + 3 + 5 + 24,
-		.vrefresh = 60,
-	},
-	{
-		.clock = 57500,
-		.hdisplay = 1280,
-		.hsync_start = 1280 + 48,
-		.hsync_end = 1280 + 48 + 32,
-		.htotal = 1280 + 48 + 32 + 80,
-		.vdisplay = 800,
-		.vsync_start = 800 + 3,
-		.vsync_end = 800 + 3 + 5,
-		.vtotal = 800 + 3 + 5 + 24,
-		.vrefresh = 48,
-	},
+	SP_DISPLAY_MODE(71900, 1280, 48, 32, 80, 800, 3, 5, 24, 60, 0),
+	SP_DISPLAY_MODE(57500, 1280, 48, 32, 80, 800, 3, 5, 24, 48, 0),
 };
 
 static const struct panel_desc boe_nv101wxmn51 = {
@@ -777,19 +655,9 @@ static const struct panel_desc boe_nv101wxmn51 = {
 	},
 };
 
-static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
-	.clock = 66770,
-	.hdisplay = 800,
-	.hsync_start = 800 + 49,
-	.hsync_end = 800 + 49 + 33,
-	.htotal = 800 + 49 + 33 + 17,
-	.vdisplay = 1280,
-	.vsync_start = 1280 + 1,
-	.vsync_end = 1280 + 1 + 7,
-	.vtotal = 1280 + 1 + 7 + 15,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode chunghwa_claa070wp03xg_mode =
+	SP_DISPLAY_MODE(66770, 800, 49, 33, 17, 1280, 1, 7, 15, 60,
+			DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 static const struct panel_desc chunghwa_claa070wp03xg = {
 	.modes = &chunghwa_claa070wp03xg_mode,
@@ -801,18 +669,8 @@ static const struct panel_desc chunghwa_claa070wp03xg = {
 	},
 };
 
-static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
-	.clock = 72070,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 58,
-	.hsync_end = 1366 + 58 + 58,
-	.htotal = 1366 + 58 + 58 + 58,
-	.vdisplay = 768,
-	.vsync_start = 768 + 4,
-	.vsync_end = 768 + 4 + 4,
-	.vtotal = 768 + 4 + 4 + 4,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode chunghwa_claa101wa01a_mode =
+	SP_DISPLAY_MODE(72070, 1366, 58, 58, 58, 768, 4, 4, 4, 60, 0);
 
 static const struct panel_desc chunghwa_claa101wa01a = {
 	.modes = &chunghwa_claa101wa01a_mode,
@@ -824,18 +682,8 @@ static const struct panel_desc chunghwa_claa101wa01a = {
 	},
 };
 
-static const struct drm_display_mode chunghwa_claa101wb01_mode = {
-	.clock = 69300,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 48,
-	.hsync_end = 1366 + 48 + 32,
-	.htotal = 1366 + 48 + 32 + 20,
-	.vdisplay = 768,
-	.vsync_start = 768 + 16,
-	.vsync_end = 768 + 16 + 8,
-	.vtotal = 768 + 16 + 8 + 16,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode chunghwa_claa101wb01_mode =
+	SP_DISPLAY_MODE(69300, 1366, 48, 32, 20, 768, 16, 8, 16, 60, 0);
 
 static const struct panel_desc chunghwa_claa101wb01 = {
 	.modes = &chunghwa_claa101wb01_mode,
@@ -847,19 +695,9 @@ static const struct panel_desc chunghwa_claa101wb01 = {
 	},
 };
 
-static const struct drm_display_mode edt_et057090dhu_mode = {
-	.clock = 25175,
-	.hdisplay = 640,
-	.hsync_start = 640 + 16,
-	.hsync_end = 640 + 16 + 30,
-	.htotal = 640 + 16 + 30 + 114,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 3,
-	.vtotal = 480 + 10 + 3 + 32,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode edt_et057090dhu_mode =
+	SP_DISPLAY_MODE(25175, 640, 16, 30, 114, 480, 10, 3, 32, 60,
+			DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 static const struct panel_desc edt_et057090dhu = {
 	.modes = &edt_et057090dhu_mode,
@@ -873,19 +711,9 @@ static const struct panel_desc edt_et057090dhu = {
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
 };
 
-static const struct drm_display_mode edt_etm0700g0dh6_mode = {
-	.clock = 33260,
-	.hdisplay = 800,
-	.hsync_start = 800 + 40,
-	.hsync_end = 800 + 40 + 128,
-	.htotal = 800 + 40 + 128 + 88,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 2,
-	.vtotal = 480 + 10 + 2 + 33,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
+static const struct drm_display_mode edt_etm0700g0dh6_mode =
+	SP_DISPLAY_MODE(33260, 800, 40, 128, 88, 480, 10, 2, 33, 60,
+			DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
 
 static const struct panel_desc edt_etm0700g0dh6 = {
 	.modes = &edt_etm0700g0dh6_mode,
@@ -899,18 +727,8 @@ static const struct panel_desc edt_etm0700g0dh6 = {
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
 };
 
-static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
-	.clock = 32260,
-	.hdisplay = 800,
-	.hsync_start = 800 + 168,
-	.hsync_end = 800 + 168 + 64,
-	.htotal = 800 + 168 + 64 + 88,
-	.vdisplay = 480,
-	.vsync_start = 480 + 37,
-	.vsync_end = 480 + 37 + 2,
-	.vtotal = 480 + 37 + 2 + 8,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode =
+	SP_DISPLAY_MODE(32260, 800, 168, 64, 88, 480, 37, 2, 8, 60, 0);
 
 static const struct panel_desc foxlink_fl500wvr00_a0t = {
 	.modes = &foxlink_fl500wvr00_a0t_mode,
@@ -923,18 +741,8 @@ static const struct panel_desc foxlink_fl500wvr00_a0t = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 };
 
-static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 5,
-	.hsync_end = 480 + 5 + 1,
-	.htotal = 480 + 5 + 1 + 40,
-	.vdisplay = 272,
-	.vsync_start = 272 + 8,
-	.vsync_end = 272 + 8 + 1,
-	.vtotal = 272 + 8 + 1 + 8,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode giantplus_gpg482739qs5_mode =
+	SP_DISPLAY_MODE(9000, 480, 5, 1, 40, 272, 8, 1, 8, 60, 0);
 
 static const struct panel_desc giantplus_gpg482739qs5 = {
 	.modes = &giantplus_gpg482739qs5_mode,
@@ -1000,18 +808,8 @@ static const struct panel_desc hannstar_hsd100pxn1 = {
 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 };
 
-static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
-	.clock = 33333,
-	.hdisplay = 800,
-	.hsync_start = 800 + 85,
-	.hsync_end = 800 + 85 + 86,
-	.htotal = 800 + 85 + 86 + 85,
-	.vdisplay = 480,
-	.vsync_start = 480 + 16,
-	.vsync_end = 480 + 16 + 13,
-	.vtotal = 480 + 16 + 13 + 16,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode hitachi_tx23d38vm0caa_mode =
+	SP_DISPLAY_MODE(33333, 800, 85, 86, 85, 480, 16, 13, 16, 60, 0);
 
 static const struct panel_desc hitachi_tx23d38vm0caa = {
 	.modes = &hitachi_tx23d38vm0caa_mode,
@@ -1023,19 +821,9 @@ static const struct panel_desc hitachi_tx23d38vm0caa = {
 	},
 };
 
-static const struct drm_display_mode innolux_at043tn24_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 2,
-	.hsync_end = 480 + 2 + 41,
-	.htotal = 480 + 2 + 41 + 2,
-	.vdisplay = 272,
-	.vsync_start = 272 + 2,
-	.vsync_end = 272 + 2 + 11,
-	.vtotal = 272 + 2 + 11 + 2,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
+static const struct drm_display_mode innolux_at043tn24_mode =
+	SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 11, 2, 60,
+			DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
 
 static const struct panel_desc innolux_at043tn24 = {
 	.modes = &innolux_at043tn24_mode,
@@ -1048,18 +836,8 @@ static const struct panel_desc innolux_at043tn24 = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 };
 
-static const struct drm_display_mode innolux_at070tn92_mode = {
-	.clock = 33333,
-	.hdisplay = 800,
-	.hsync_start = 800 + 210,
-	.hsync_end = 800 + 210 + 20,
-	.htotal = 800 + 210 + 20 + 46,
-	.vdisplay = 480,
-	.vsync_start = 480 + 22,
-	.vsync_end = 480 + 22 + 10,
-	.vtotal = 480 + 22 + 23 + 10,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode innolux_at070tn92_mode =
+	SP_DISPLAY_MODE(33333, 800, 210, 20, 46, 480, 22, 10, 23, 60, 0);
 
 static const struct panel_desc innolux_at070tn92 = {
 	.modes = &innolux_at070tn92_mode,
@@ -1126,19 +904,9 @@ static const struct panel_desc innolux_g121i1_l01 = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 };
 
-static const struct drm_display_mode innolux_g121x1_l03_mode = {
-	.clock = 65000,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 0,
-	.hsync_end = 1024 + 1,
-	.htotal = 1024 + 0 + 1 + 320,
-	.vdisplay = 768,
-	.vsync_start = 768 + 38,
-	.vsync_end = 768 + 38 + 1,
-	.vtotal = 768 + 38 + 1 + 0,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
+static const struct drm_display_mode innolux_g121x1_l03_mode =
+	SP_DISPLAY_MODE(65000, 1024, 0, 1, 320, 768, 38, 1, 0, 60,
+			DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
 
 static const struct panel_desc innolux_g121x1_l03 = {
 	.modes = &innolux_g121x1_l03_mode,
@@ -1155,19 +923,9 @@ static const struct panel_desc innolux_g121x1_l03 = {
 	},
 };
 
-static const struct drm_display_mode innolux_n116bge_mode = {
-	.clock = 76420,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 136,
-	.hsync_end = 1366 + 136 + 30,
-	.htotal = 1366 + 136 + 30 + 60,
-	.vdisplay = 768,
-	.vsync_start = 768 + 8,
-	.vsync_end = 768 + 8 + 12,
-	.vtotal = 768 + 8 + 12 + 12,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
+static const struct drm_display_mode innolux_n116bge_mode =
+	SP_DISPLAY_MODE(76420, 1366, 136, 30, 60, 768, 8, 12, 12, 60,
+			DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
 
 static const struct panel_desc innolux_n116bge = {
 	.modes = &innolux_n116bge_mode,
@@ -1179,18 +937,8 @@ static const struct panel_desc innolux_n116bge = {
 	},
 };
 
-static const struct drm_display_mode innolux_n156bge_l21_mode = {
-	.clock = 69300,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 16,
-	.hsync_end = 1366 + 16 + 34,
-	.htotal = 1366 + 16 + 34 + 50,
-	.vdisplay = 768,
-	.vsync_start = 768 + 2,
-	.vsync_end = 768 + 2 + 6,
-	.vtotal = 768 + 2 + 6 + 12,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode innolux_n156bge_l21_mode =
+	SP_DISPLAY_MODE(69300, 1366, 16, 34, 50, 768, 2, 6, 12, 60, 0);
 
 static const struct panel_desc innolux_n156bge_l21 = {
 	.modes = &innolux_n156bge_l21_mode,
@@ -1202,18 +950,8 @@ static const struct panel_desc innolux_n156bge_l21 = {
 	},
 };
 
-static const struct drm_display_mode innolux_zj070na_01p_mode = {
-	.clock = 51501,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 128,
-	.hsync_end = 1024 + 128 + 64,
-	.htotal = 1024 + 128 + 64 + 128,
-	.vdisplay = 600,
-	.vsync_start = 600 + 16,
-	.vsync_end = 600 + 16 + 4,
-	.vtotal = 600 + 16 + 4 + 16,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode innolux_zj070na_01p_mode =
+	SP_DISPLAY_MODE(51501, 1024, 128, 64, 128, 600, 16, 4, 16, 60, 0);
 
 static const struct panel_desc innolux_zj070na_01p = {
 	.modes = &innolux_zj070na_01p_mode,
@@ -1249,18 +987,8 @@ static const struct panel_desc kyo_tcg121xglp = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 };
 
-static const struct drm_display_mode lg_lb070wv8_mode = {
-	.clock = 33246,
-	.hdisplay = 800,
-	.hsync_start = 800 + 88,
-	.hsync_end = 800 + 88 + 80,
-	.htotal = 800 + 88 + 80 + 88,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 25,
-	.vtotal = 480 + 10 + 25 + 10,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode lg_lb070wv8_mode =
+	SP_DISPLAY_MODE(33246, 800, 88, 80, 88, 480, 10, 25, 10, 60, 0);
 
 static const struct panel_desc lg_lb070wv8 = {
 	.modes = &lg_lb070wv8_mode,
@@ -1273,19 +1001,9 @@ static const struct panel_desc lg_lb070wv8 = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 };
 
-static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
-	.clock = 200000,
-	.hdisplay = 1536,
-	.hsync_start = 1536 + 12,
-	.hsync_end = 1536 + 12 + 16,
-	.htotal = 1536 + 12 + 16 + 48,
-	.vdisplay = 2048,
-	.vsync_start = 2048 + 8,
-	.vsync_end = 2048 + 8 + 4,
-	.vtotal = 2048 + 8 + 4 + 8,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode lg_lp079qx1_sp0v_mode =
+	SP_DISPLAY_MODE(200000, 1536, 12, 16, 48, 2048, 8, 4, 8, 60,
+			 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 static const struct panel_desc lg_lp079qx1_sp0v = {
 	.modes = &lg_lp079qx1_sp0v_mode,
@@ -1296,18 +1014,8 @@ static const struct panel_desc lg_lp079qx1_sp0v = {
 	},
 };
 
-static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
-	.clock = 205210,
-	.hdisplay = 2048,
-	.hsync_start = 2048 + 150,
-	.hsync_end = 2048 + 150 + 5,
-	.htotal = 2048 + 150 + 5 + 5,
-	.vdisplay = 1536,
-	.vsync_start = 1536 + 3,
-	.vsync_end = 1536 + 3 + 1,
-	.vtotal = 1536 + 3 + 1 + 9,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode lg_lp097qx1_spa1_mode =
+	SP_DISPLAY_MODE(205210, 2048, 150, 5, 5, 1536, 3, 1, 9, 60, 0);
 
 static const struct panel_desc lg_lp097qx1_spa1 = {
 	.modes = &lg_lp097qx1_spa1_mode,
@@ -1318,18 +1026,8 @@ static const struct panel_desc lg_lp097qx1_spa1 = {
 	},
 };
 
-static const struct drm_display_mode lg_lp120up1_mode = {
-	.clock = 162300,
-	.hdisplay = 1920,
-	.hsync_start = 1920 + 40,
-	.hsync_end = 1920 + 40 + 40,
-	.htotal = 1920 + 40 + 40+ 80,
-	.vdisplay = 1280,
-	.vsync_start = 1280 + 4,
-	.vsync_end = 1280 + 4 + 4,
-	.vtotal = 1280 + 4 + 4 + 12,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode lg_lp120up1_mode =
+	SP_DISPLAY_MODE(162300, 1920, 40, 40, 80, 1280, 4, 4, 12, 60, 0);
 
 static const struct panel_desc lg_lp120up1 = {
 	.modes = &lg_lp120up1_mode,
@@ -1341,18 +1039,8 @@ static const struct panel_desc lg_lp120up1 = {
 	},
 };
 
-static const struct drm_display_mode lg_lp129qe_mode = {
-	.clock = 285250,
-	.hdisplay = 2560,
-	.hsync_start = 2560 + 48,
-	.hsync_end = 2560 + 48 + 32,
-	.htotal = 2560 + 48 + 32 + 80,
-	.vdisplay = 1700,
-	.vsync_start = 1700 + 3,
-	.vsync_end = 1700 + 3 + 10,
-	.vtotal = 1700 + 3 + 10 + 36,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode lg_lp129qe_mode =
+	SP_DISPLAY_MODE(285250, 2560, 48, 32, 80, 1700, 3, 10, 36, 60, 0);
 
 static const struct panel_desc lg_lp129qe = {
 	.modes = &lg_lp129qe_mode,
@@ -1391,19 +1079,9 @@ static const struct panel_desc nec_nl12880bc20_05 = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 };
 
-static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
-	.clock = 10870,
-	.hdisplay = 480,
-	.hsync_start = 480 + 2,
-	.hsync_end = 480 + 2 + 41,
-	.htotal = 480 + 2 + 41 + 2,
-	.vdisplay = 272,
-	.vsync_start = 272 + 2,
-	.vsync_end = 272 + 2 + 4,
-	.vtotal = 272 + 2 + 4 + 2,
-	.vrefresh = 74,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode nec_nl4827hc19_05b_mode =
+	SP_DISPLAY_MODE(10870, 480, 2, 41, 2, 272, 2, 4, 2, 74,
+			 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 static const struct panel_desc nec_nl4827hc19_05b = {
 	.modes = &nec_nl4827hc19_05b_mode,
@@ -1417,18 +1095,8 @@ static const struct panel_desc nec_nl4827hc19_05b = {
 	.bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
 };
 
-static const struct drm_display_mode netron_dy_e231732_mode = {
-	.clock = 66000,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 160,
-	.hsync_end = 1024 + 160 + 70,
-	.htotal = 1024 + 160 + 70 + 90,
-	.vdisplay = 600,
-	.vsync_start = 600 + 127,
-	.vsync_end = 600 + 127 + 20,
-	.vtotal = 600 + 127 + 20 + 3,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode netron_dy_e231732_mode =
+	SP_DISPLAY_MODE(66000, 1024, 160, 70, 90, 600, 127, 20, 3, 60, 0);
 
 static const struct panel_desc netron_dy_e231732 = {
 	.modes = &netron_dy_e231732_mode,
@@ -1466,17 +1134,8 @@ static const struct panel_desc nlt_nl192108ac18_02d = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 };
 
-static const struct drm_display_mode nvd_9128_mode = {
-	.clock = 29500,
-	.hdisplay = 800,
-	.hsync_start = 800 + 130,
-	.hsync_end = 800 + 130 + 98,
-	.htotal = 800 + 0 + 130 + 98,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 50,
-	.vtotal = 480 + 0 + 10 + 50,
-};
+static const struct drm_display_mode nvd_9128_mode =
+	SP_DISPLAY_MODE(29500, 800, 130, 98, 0, 480, 10, 50, 0, 0, 0);
 
 static const struct panel_desc nvd_9128 = {
 	.modes = &nvd_9128_mode,
@@ -1519,18 +1178,8 @@ static const struct panel_desc okaya_rs800480t_7x0gp = {
 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 };
 
-static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 5,
-	.hsync_end = 480 + 5 + 30,
-	.htotal = 480 + 5 + 30 + 10,
-	.vdisplay = 272,
-	.vsync_start = 272 + 8,
-	.vsync_end = 272 + 8 + 5,
-	.vtotal = 272 + 8 + 5 + 3,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode =
+	SP_DISPLAY_MODE(9000, 480, 5, 30, 10, 272, 8, 5, 3, 60, 0);
 
 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
 	.modes = &olimex_lcd_olinuxino_43ts_mode,
@@ -1547,19 +1196,9 @@ static const struct panel_desc olimex_lcd_olinuxino_43ts = {
  * pixel clocks, but this is the timing that was being used in the Adafruit
  * installation instructions.
  */
-static const struct drm_display_mode ontat_yx700wv03_mode = {
-	.clock = 29500,
-	.hdisplay = 800,
-	.hsync_start = 824,
-	.hsync_end = 896,
-	.htotal = 992,
-	.vdisplay = 480,
-	.vsync_start = 483,
-	.vsync_end = 493,
-	.vtotal = 500,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode ontat_yx700wv03_mode =
+	SP_DISPLAY_MODE(29500, 800, 24, 72, 96, 480, 3, 10, 7, 60,
+			DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 /*
  * Specification at:
@@ -1576,18 +1215,8 @@ static const struct panel_desc ontat_yx700wv03 = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 };
 
-static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
-	.clock = 25000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 10,
-	.hsync_end = 480 + 10 + 10,
-	.htotal = 480 + 10 + 10 + 15,
-	.vdisplay = 800,
-	.vsync_start = 800 + 3,
-	.vsync_end = 800 + 3 + 3,
-	.vtotal = 800 + 3 + 3 + 3,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode ortustech_com43h4m85ulc_mode  =
+	SP_DISPLAY_MODE(25000, 480, 10, 10, 15, 800, 3, 3, 3, 60, 0);
 
 static const struct panel_desc ortustech_com43h4m85ulc = {
 	.modes = &ortustech_com43h4m85ulc_mode,
@@ -1601,18 +1230,8 @@ static const struct panel_desc ortustech_com43h4m85ulc = {
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
 };
 
-static const struct drm_display_mode qd43003c0_40_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 8,
-	.hsync_end = 480 + 8 + 4,
-	.htotal = 480 + 8 + 4 + 39,
-	.vdisplay = 272,
-	.vsync_start = 272 + 4,
-	.vsync_end = 272 + 4 + 10,
-	.vtotal = 272 + 4 + 10 + 2,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode qd43003c0_40_mode =
+	SP_DISPLAY_MODE(9000, 480, 8, 4, 39, 272, 4, 10, 2, 60, 0);
 
 static const struct panel_desc qd43003c0_40 = {
 	.modes = &qd43003c0_40_mode,
@@ -1625,18 +1244,8 @@ static const struct panel_desc qd43003c0_40 = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 };
 
-static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
-	.clock = 271560,
-	.hdisplay = 2560,
-	.hsync_start = 2560 + 48,
-	.hsync_end = 2560 + 48 + 32,
-	.htotal = 2560 + 48 + 32 + 80,
-	.vdisplay = 1600,
-	.vsync_start = 1600 + 2,
-	.vsync_end = 1600 + 2 + 5,
-	.vtotal = 1600 + 2 + 5 + 57,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode samsung_lsn122dl01_c01_mode =
+	SP_DISPLAY_MODE(271560, 2560, 48, 32, 80, 1600, 2, 5, 57, 60, 0);
 
 static const struct panel_desc samsung_lsn122dl01_c01 = {
 	.modes = &samsung_lsn122dl01_c01_mode,
@@ -1647,18 +1256,8 @@ static const struct panel_desc samsung_lsn122dl01_c01 = {
 	},
 };
 
-static const struct drm_display_mode samsung_ltn101nt05_mode = {
-	.clock = 54030,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 24,
-	.hsync_end = 1024 + 24 + 136,
-	.htotal = 1024 + 24 + 136 + 160,
-	.vdisplay = 600,
-	.vsync_start = 600 + 3,
-	.vsync_end = 600 + 3 + 6,
-	.vtotal = 600 + 3 + 6 + 61,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode samsung_ltn101nt05_mode =
+	SP_DISPLAY_MODE(54030, 1024, 24, 136, 160, 600, 3, 6, 61, 60, 0);
 
 static const struct panel_desc samsung_ltn101nt05 = {
 	.modes = &samsung_ltn101nt05_mode,
@@ -1670,18 +1269,8 @@ static const struct panel_desc samsung_ltn101nt05 = {
 	},
 };
 
-static const struct drm_display_mode samsung_ltn140at29_301_mode = {
-	.clock = 76300,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 64,
-	.hsync_end = 1366 + 64 + 48,
-	.htotal = 1366 + 64 + 48 + 128,
-	.vdisplay = 768,
-	.vsync_start = 768 + 2,
-	.vsync_end = 768 + 2 + 5,
-	.vtotal = 768 + 2 + 5 + 17,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode samsung_ltn140at29_301_mode =
+	SP_DISPLAY_MODE(76300, 1366, 64, 48, 128, 768, 2, 5, 17, 60, 0);
 
 static const struct panel_desc samsung_ltn140at29_301 = {
 	.modes = &samsung_ltn140at29_301_mode,
@@ -1717,19 +1306,9 @@ static const struct panel_desc sharp_lq101k1ly04 = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 };
 
-static const struct drm_display_mode sharp_lq123p1jx31_mode = {
-	.clock = 252750,
-	.hdisplay = 2400,
-	.hsync_start = 2400 + 48,
-	.hsync_end = 2400 + 48 + 32,
-	.htotal = 2400 + 48 + 32 + 80,
-	.vdisplay = 1600,
-	.vsync_start = 1600 + 3,
-	.vsync_end = 1600 + 3 + 10,
-	.vtotal = 1600 + 3 + 10 + 33,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode sharp_lq123p1jx31_mode =
+	SP_DISPLAY_MODE(252750, 2400, 48, 32, 80, 1600, 3, 10, 33, 60,
+			 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 static const struct panel_desc sharp_lq123p1jx31 = {
 	.modes = &sharp_lq123p1jx31_mode,
@@ -1746,18 +1325,8 @@ static const struct panel_desc sharp_lq123p1jx31 = {
 	},
 };
 
-static const struct drm_display_mode sharp_lq150x1lg11_mode = {
-	.clock = 71100,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 168,
-	.hsync_end = 1024 + 168 + 64,
-	.htotal = 1024 + 168 + 64 + 88,
-	.vdisplay = 768,
-	.vsync_start = 768 + 37,
-	.vsync_end = 768 + 37 + 2,
-	.vtotal = 768 + 37 + 2 + 8,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode sharp_lq150x1lg11_mode =
+	SP_DISPLAY_MODE(71100, 1024, 168, 64, 88, 768, 37, 2, 8, 60, 0);
 
 static const struct panel_desc sharp_lq150x1lg11 = {
 	.modes = &sharp_lq150x1lg11_mode,
@@ -1770,18 +1339,8 @@ static const struct panel_desc sharp_lq150x1lg11 = {
 	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
 };
 
-static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
-	.clock = 33300,
-	.hdisplay = 800,
-	.hsync_start = 800 + 1,
-	.hsync_end = 800 + 1 + 64,
-	.htotal = 800 + 1 + 64 + 64,
-	.vdisplay = 480,
-	.vsync_start = 480 + 1,
-	.vsync_end = 480 + 1 + 23,
-	.vtotal = 480 + 1 + 23 + 22,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode =
+	SP_DISPLAY_MODE(33300, 800, 1, 64, 64, 480, 1, 23, 22, 60, 0);
 
 static const struct panel_desc shelly_sca07010_bfn_lnn = {
 	.modes = &shelly_sca07010_bfn_lnn_mode,
@@ -1793,19 +1352,9 @@ static const struct panel_desc shelly_sca07010_bfn_lnn = {
 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 };
 
-static const struct drm_display_mode starry_kr122ea0sra_mode = {
-	.clock = 147000,
-	.hdisplay = 1920,
-	.hsync_start = 1920 + 16,
-	.hsync_end = 1920 + 16 + 16,
-	.htotal = 1920 + 16 + 16 + 32,
-	.vdisplay = 1200,
-	.vsync_start = 1200 + 15,
-	.vsync_end = 1200 + 15 + 2,
-	.vtotal = 1200 + 15 + 2 + 18,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode starry_kr122ea0sra_mode =
+	SP_DISPLAY_MODE(147000, 1920, 16, 16, 32, 1200, 15, 2, 18, 60,
+			 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 static const struct panel_desc starry_kr122ea0sra = {
 	.modes = &starry_kr122ea0sra_mode,
@@ -1845,18 +1394,8 @@ static const struct panel_desc tianma_tm070jdhg30 = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 };
 
-static const struct drm_display_mode tpk_f07a_0102_mode = {
-	.clock = 33260,
-	.hdisplay = 800,
-	.hsync_start = 800 + 40,
-	.hsync_end = 800 + 40 + 128,
-	.htotal = 800 + 40 + 128 + 88,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 2,
-	.vtotal = 480 + 10 + 2 + 33,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode tpk_f07a_0102_mode =
+	SP_DISPLAY_MODE(33260, 800, 40, 128, 88, 480, 10, 2, 33, 60, 0);
 
 static const struct panel_desc tpk_f07a_0102 = {
 	.modes = &tpk_f07a_0102_mode,
@@ -1868,18 +1407,8 @@ static const struct panel_desc tpk_f07a_0102 = {
 	.bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
 };
 
-static const struct drm_display_mode tpk_f10a_0102_mode = {
-	.clock = 45000,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 176,
-	.hsync_end = 1024 + 176 + 5,
-	.htotal = 1024 + 176 + 5 + 88,
-	.vdisplay = 600,
-	.vsync_start = 600 + 20,
-	.vsync_end = 600 + 20 + 5,
-	.vtotal = 600 + 20 + 5 + 25,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode tpk_f10a_0102_mode =
+	SP_DISPLAY_MODE(45000, 1024, 176, 5, 88, 600, 20, 5, 25, 60, 0);
 
 static const struct panel_desc tpk_f10a_0102 = {
 	.modes = &tpk_f10a_0102_mode,
@@ -1926,19 +1455,9 @@ static const struct panel_desc urt_umsh_8596md_parallel = {
 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 };
 
-static const struct drm_display_mode winstar_wf35ltiacd_mode = {
-	.clock = 6410,
-	.hdisplay = 320,
-	.hsync_start = 320 + 20,
-	.hsync_end = 320 + 20 + 30,
-	.htotal = 320 + 20 + 30 + 38,
-	.vdisplay = 240,
-	.vsync_start = 240 + 4,
-	.vsync_end = 240 + 4 + 3,
-	.vtotal = 240 + 4 + 3 + 15,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode winstar_wf35ltiacd_mode =
+	SP_DISPLAY_MODE(6410, 320, 20, 30, 38, 240, 4, 3, 15, 60,
+			DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 static const struct panel_desc winstar_wf35ltiacd = {
 	.modes = &winstar_wf35ltiacd_mode,
@@ -2198,18 +1717,8 @@ struct panel_desc_dsi {
 	unsigned int lanes;
 };
 
-static const struct drm_display_mode auo_b080uan01_mode = {
-	.clock = 154500,
-	.hdisplay = 1200,
-	.hsync_start = 1200 + 62,
-	.hsync_end = 1200 + 62 + 4,
-	.htotal = 1200 + 62 + 4 + 62,
-	.vdisplay = 1920,
-	.vsync_start = 1920 + 9,
-	.vsync_end = 1920 + 9 + 2,
-	.vtotal = 1920 + 9 + 2 + 8,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode auo_b080uan01_mode =
+	SP_DISPLAY_MODE(154500, 1200, 62, 4, 62, 1920, 9, 2, 8, 60, 0);
 
 static const struct panel_desc_dsi auo_b080uan01 = {
 	.desc = {
@@ -2226,19 +1735,9 @@ static const struct panel_desc_dsi auo_b080uan01 = {
 	.lanes = 4,
 };
 
-static const struct drm_display_mode boe_tv080wum_nl0_mode = {
-	.clock = 160000,
-	.hdisplay = 1200,
-	.hsync_start = 1200 + 120,
-	.hsync_end = 1200 + 120 + 20,
-	.htotal = 1200 + 120 + 20 + 21,
-	.vdisplay = 1920,
-	.vsync_start = 1920 + 21,
-	.vsync_end = 1920 + 21 + 3,
-	.vtotal = 1920 + 21 + 3 + 18,
-	.vrefresh = 60,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
+static const struct drm_display_mode boe_tv080wum_nl0_mode =
+	SP_DISPLAY_MODE(160000, 1200, 120, 20, 21, 1920, 21, 3, 18, 60,
+			 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 
 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
 	.desc = {
@@ -2256,18 +1755,8 @@ static const struct panel_desc_dsi boe_tv080wum_nl0 = {
 	.lanes = 4,
 };
 
-static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
-	.clock = 71000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 32,
-	.hsync_end = 800 + 32 + 1,
-	.htotal = 800 + 32 + 1 + 57,
-	.vdisplay = 1280,
-	.vsync_start = 1280 + 28,
-	.vsync_end = 1280 + 28 + 1,
-	.vtotal = 1280 + 28 + 1 + 14,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode lg_ld070wx3_sl01_mode =
+	SP_DISPLAY_MODE(71000, 800, 32, 1, 57, 1280, 28, 1, 14, 60, 0);
 
 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
 	.desc = {
@@ -2284,18 +1773,8 @@ static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
 	.lanes = 4,
 };
 
-static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
-	.clock = 67000,
-	.hdisplay = 720,
-	.hsync_start = 720 + 12,
-	.hsync_end = 720 + 12 + 4,
-	.htotal = 720 + 12 + 4 + 112,
-	.vdisplay = 1280,
-	.vsync_start = 1280 + 8,
-	.vsync_end = 1280 + 8 + 4,
-	.vtotal = 1280 + 8 + 4 + 12,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode lg_lh500wx1_sd03_mode =
+	SP_DISPLAY_MODE(67000, 720, 12, 4, 112, 1280, 8, 4, 12, 60, 0);
 
 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
 	.desc = {
@@ -2312,18 +1791,8 @@ static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
 	.lanes = 4,
 };
 
-static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
-	.clock = 157200,
-	.hdisplay = 1920,
-	.hsync_start = 1920 + 154,
-	.hsync_end = 1920 + 154 + 16,
-	.htotal = 1920 + 154 + 16 + 32,
-	.vdisplay = 1200,
-	.vsync_start = 1200 + 17,
-	.vsync_end = 1200 + 17 + 2,
-	.vtotal = 1200 + 17 + 2 + 16,
-	.vrefresh = 60,
-};
+static const struct drm_display_mode panasonic_vvx10f004b00_mode =
+	SP_DISPLAY_MODE(157200, 1920, 154, 16, 32, 1200, 17, 2, 16, 60, 0);
 
 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
 	.desc = {
-- 
2.1.4

[PATCH 3/9] drm/panel: simple: make it possible to override LCD bus format

[Lothar Waßmann]

The baseboards for the Ka-Ro electronics series of i.MX modules
use a 24bit LCD interface, no matter what LCD bus width the SoC on the
module provides and what the LCD panel expects. LCDs with 6bit per color
will ignore the 2 LSBs of each color lane, and modules using a SoC
that provides only 6bit per color, drive the display information on the
6 MSBs of each color lane and tie the 2 LSBs of each color lane to GND.

Thus, no matter what combination of LCD and SoC is used, the LCD port
can be used without shuffling bit lanes by always configuring the LCD
output to 24bit mode.

Add a function to handle certain quirks of the LCD interface to the
panel driver to be able to override the bus format specified in a
panel's display_mode.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
---
 .../bindings/display/panel/simple-panel.txt        |  2 ++
 drivers/gpu/drm/panel/panel-simple.c               | 40 +++++++++++++++++++++-
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/panel/simple-panel.txt b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
index 1341bbf..e2308c3 100644
--- a/Documentation/devicetree/bindings/display/panel/simple-panel.txt
+++ b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
@@ -7,6 +7,8 @@ Optional properties:
 - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
 - enable-gpios: GPIO pin to enable or disable the panel
 - backlight: phandle of the backlight device attached to the panel
+- bus-format-override: override the bus_format setting of the panel's
+  display_mode settings
 
 Example:
 
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index fde9c41..f356a7b 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -87,6 +87,8 @@ struct panel_simple {
 	struct i2c_adapter *ddc;
 
 	struct gpio_desc *enable_gpio;
+
+	u32 bus_fmt_override;
 };
 
 #define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
@@ -165,7 +167,11 @@ static int panel_simple_get_fixed_modes(struct panel_simple *panel)
 	connector->display_info.bpc = panel->desc->bpc;
 	connector->display_info.width_mm = panel->desc->size.width;
 	connector->display_info.height_mm = panel->desc->size.height;
-	if (panel->desc->bus_format)
+
+	if (panel->bus_fmt_override)
+		drm_display_info_set_bus_formats(&connector->display_info,
+						 &panel->bus_fmt_override, 1);
+	else if (panel->desc->bus_format)
 		drm_display_info_set_bus_formats(&connector->display_info,
 						 &panel->desc->bus_format, 1);
 	connector->display_info.bus_flags = panel->desc->bus_flags;
@@ -298,6 +304,34 @@ static int panel_simple_get_timings(struct drm_panel *panel,
 	return p->desc->num_timings;
 }
 
+static inline int panel_simple_check_quirks(struct device *dev,
+					    struct panel_simple *p)
+{
+	const char *bus_fmt;
+
+	if (of_property_read_string(dev->of_node, "bus-format-override",
+				    &bus_fmt) == 0) {
+		if (strcmp(bus_fmt, "rgb24") == 0)
+			p->bus_fmt_override = MEDIA_BUS_FMT_RGB888_1X24;
+		else if (strcmp(bus_fmt, "rgb666") == 0)
+			p->bus_fmt_override = MEDIA_BUS_FMT_RGB666_1X18;
+		else if (strcmp(bus_fmt, "rgb565") == 0)
+			p->bus_fmt_override = MEDIA_BUS_FMT_RGB565_1X16;
+		else if (strcmp(bus_fmt, "spwg-18") == 0)
+			p->bus_fmt_override = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG;
+		else if (strcmp(bus_fmt, "spwg-24") == 0)
+			p->bus_fmt_override = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG;
+		else if (strcmp(bus_fmt, "jeida-24") == 0)
+			p->bus_fmt_override = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
+		else
+			dev_err(dev,
+				"Unsupported bus-format-override value: '%s'\n",
+				bus_fmt);
+		return p->bus_fmt_override ? 0 : -EINVAL;
+	}
+	return 0;
+}
+
 static const struct drm_panel_funcs panel_simple_funcs = {
 	.disable = panel_simple_disable,
 	.unprepare = panel_simple_unprepare,
@@ -353,6 +387,10 @@ static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 		}
 	}
 
+	err = panel_simple_check_quirks(dev, panel);
+	if (err)
+		goto free_ddc;
+
 	drm_panel_init(&panel->base);
 	panel->base.dev = dev;
 	panel->base.funcs = &panel_simple_funcs;
-- 
2.1.4

[PATCH 4/9] drm/panel: simple: add support for overriding the pixel clock polarity

[Lothar Waßmann]

The Ka-Ro electronics MB7 baseboard has an on-board LCD->LVDS
converter that requires a fixed pixelclk polarity, no matter what the
panel's display_mode specifies. Add an option to override the pixelclk
polarity defined in the panel's display_mode via DTB.

Signed-off-by: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
---
 .../bindings/display/panel/simple-panel.txt        |  3 +++
 drivers/gpu/drm/panel/panel-simple.c               | 30 ++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/panel/simple-panel.txt b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
index e2308c3..dcaf9a7 100644
--- a/Documentation/devicetree/bindings/display/panel/simple-panel.txt
+++ b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
@@ -9,6 +9,9 @@ Optional properties:
 - backlight: phandle of the backlight device attached to the panel
 - bus-format-override: override the bus_format setting of the panel's
   display_mode settings
+- pixelclk-active: override the pixelclock polarity defined in the
+  panel's display_mode settings
+
 
 Example:
 
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index f356a7b..7bbb752 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -89,6 +89,12 @@ struct panel_simple {
 	struct gpio_desc *enable_gpio;
 
 	u32 bus_fmt_override;
+	u32 quirks;
+};
+
+enum {
+	PANEL_QUIRK_PIXDATA_NEGEDGE = BIT(0),
+	PANEL_QUIRK_PIXDATA_POSEDGE = BIT(1),
 };
 
 #define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
@@ -110,6 +116,15 @@ static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 	return container_of(panel, struct panel_simple, base);
 }
 
+static inline void panel_simple_apply_quirks(struct panel_simple *panel,
+					     struct drm_display_info *info)
+{
+	if (panel->quirks & PANEL_QUIRK_PIXDATA_NEGEDGE)
+		info->bus_flags |= DRM_BUS_FLAG_PIXDATA_NEGEDGE;
+	if (panel->quirks & PANEL_QUIRK_PIXDATA_POSEDGE)
+		info->bus_flags |= DRM_BUS_FLAG_PIXDATA_POSEDGE;
+}
+
 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
 {
 	struct drm_connector *connector = panel->base.connector;
@@ -175,6 +190,8 @@ static int panel_simple_get_fixed_modes(struct panel_simple *panel)
 		drm_display_info_set_bus_formats(&connector->display_info,
 						 &panel->desc->bus_format, 1);
 	connector->display_info.bus_flags = panel->desc->bus_flags;
+	if (panel->quirks)
+		panel_simple_apply_quirks(panel, &connector->display_info);
 
 	return num;
 }
@@ -308,6 +325,7 @@ static inline int panel_simple_check_quirks(struct device *dev,
 					    struct panel_simple *p)
 {
 	const char *bus_fmt;
+	u32 clkpol;
 
 	if (of_property_read_string(dev->of_node, "bus-format-override",
 				    &bus_fmt) == 0) {
@@ -329,6 +347,18 @@ static inline int panel_simple_check_quirks(struct device *dev,
 				bus_fmt);
 		return p->bus_fmt_override ? 0 : -EINVAL;
 	}
+
+	if (of_property_read_u32(dev->of_node, "pixelclk-active",
+				 &clkpol) == 0) {
+		if (clkpol & ~1) {
+			dev_err(dev,
+				"Invalid value for pixelclk-active: '%u' (should be <0> or <1>)\n",
+				clkpol);
+			return -EINVAL;
+		}
+		p->quirks |= clkpol ? PANEL_QUIRK_PIXDATA_POSEDGE :
+			PANEL_QUIRK_PIXDATA_NEGEDGE;
+	}
 	return 0;
 }
 
-- 
2.1.4

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[PATCH 5/9] drm/panel: simple: add support for EDT ET0350 3.5" QVGA panel

[Lothar Waßmann]

Signed-off-by: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
---
 .../bindings/display/panel/edt,et0350g0dh6.txt        |  7 +++++++
 drivers/gpu/drm/panel/panel-simple.c                  | 19 +++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et0350g0dh6.txt

diff --git a/Documentation/devicetree/bindings/display/panel/edt,et0350g0dh6.txt b/Documentation/devicetree/bindings/display/panel/edt,et0350g0dh6.txt
new file mode 100644
index 0000000..5546221
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/edt,et0350g0dh6.txt
@@ -0,0 +1,7 @@
+Emerging Display Technology Corp. 3.5" QVGA (320x240) TFT LCD panel
+
+Required properties:
+- compatible: should be "edt,et0350g0dh6"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 7bbb752..f57b463 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -763,6 +763,22 @@ static const struct panel_desc chunghwa_claa101wb01 = {
 	},
 };
 
+static const struct drm_display_mode edt_et0350g0dh6_mode =
+	SP_DISPLAY_MODE(6500, 320, 20, 0, 68, 240, 4, 0, 18, 60,
+			DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
+
+static const struct panel_desc edt_et0350g0dh6 = {
+	.modes = &edt_et0350g0dh6_mode,
+	.num_modes = 1,
+	.bpc = 6,
+	.size = {
+		.width = 70,
+		.height = 53,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
+};
+
 static const struct drm_display_mode edt_et057090dhu_mode =
 	SP_DISPLAY_MODE(25175, 640, 16, 30, 114, 480, 10, 3, 32, 60,
 			DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
@@ -1591,6 +1607,9 @@ static const struct of_device_id platform_of_match[] = {
 		.compatible = "chunghwa,claa101wb01",
 		.data = &chunghwa_claa101wb01
 	}, {
+		.compatible = "edt,et0350g0dh6",
+		.data = &edt_et0350g0dh6,
+	}, {
 		.compatible = "edt,et057090dhu",
 		.data = &edt_et057090dhu,
 	}, {
-- 
2.1.4

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[PATCH 6/9] drm/panel: simple: add support for EDT ET0430 4.3" HVGA panel

[Lothar Waßmann]

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
---
 .../bindings/display/panel/edt,et0430g0dh6.txt        |  7 +++++++
 drivers/gpu/drm/panel/panel-simple.c                  | 19 +++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et0430g0dh6.txt

diff --git a/Documentation/devicetree/bindings/display/panel/edt,et0430g0dh6.txt b/Documentation/devicetree/bindings/display/panel/edt,et0430g0dh6.txt
new file mode 100644
index 0000000..d1bdd1c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/edt,et0430g0dh6.txt
@@ -0,0 +1,7 @@
+Emerging Display Technology Corp. 4.3" HVGA (480x272) TFT LCD panel
+
+Required properties:
+- compatible: should be "edt,et0430g0dh6"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index f57b463..0b8fd55 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -779,6 +779,22 @@ static const struct panel_desc edt_et0350g0dh6 = {
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
 };
 
+static const struct drm_display_mode edt_et0430g0dh6_mode =
+	SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 10, 2, 60,
+			DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
+
+static const struct panel_desc edt_et0430g0dh6 = {
+	.modes = &edt_et0430g0dh6_mode,
+	.num_modes = 1,
+	.bpc = 6,
+	.size = {
+		.width = 95,
+		.height = 54,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
+};
+
 static const struct drm_display_mode edt_et057090dhu_mode =
 	SP_DISPLAY_MODE(25175, 640, 16, 30, 114, 480, 10, 3, 32, 60,
 			DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
@@ -1610,6 +1626,9 @@ static const struct of_device_id platform_of_match[] = {
 		.compatible = "edt,et0350g0dh6",
 		.data = &edt_et0350g0dh6,
 	}, {
+		.compatible = "edt,et0430g0dh6",
+		.data = &edt_et0430g0dh6,
+	}, {
 		.compatible = "edt,et057090dhu",
 		.data = &edt_et057090dhu,
 	}, {
-- 
2.1.4

[PATCH 7/9] drm/panel: simple: add support for NLT NL12880 12.1" WXGA LVDS panel

[Lothar Waßmann]

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
---
 .../bindings/display/panel/nlt,nl12880bc20.txt     | 14 +++++++
 drivers/gpu/drm/panel/panel-simple.c               | 45 ++++++++++++++++++++++
 2 files changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/nlt,nl12880bc20.txt

diff --git a/Documentation/devicetree/bindings/display/panel/nlt,nl12880bc20.txt b/Documentation/devicetree/bindings/display/panel/nlt,nl12880bc20.txt
new file mode 100644
index 0000000..071b065
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/nlt,nl12880bc20.txt
@@ -0,0 +1,14 @@
+NLT Technologies Ltd. NL12880BC20 12.1" WXGA LVDS panel
+
+Note: The output format of the display can be configured via two
+      control pins (FRC, MSL). Depending on the strapping of those
+      pins the appropriate 'compatible' string has to be used.
+
+Required properties:
+- compatible: should be one of:
+   - "nlt,nl12880bc20-spwg-18" for SPWG (18bpp) FRC: Low or open, MSL: Low or open
+   - "nlt,nl12880bc20-spwg-24" for SPWG (24bpp) FRC: High, MSL: High
+   - "nlt,nl12880bc20-jeida" for JEIDA          FRC: High, MSL: High
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 0b8fd55..52e0cb6 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1234,6 +1234,42 @@ static const struct panel_desc nlt_nl192108ac18_02d = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 };
 
+static const struct drm_display_mode nlt_nl12880bc20_mode =
+	SP_DISPLAY_MODE(71000, 1280, 50, 60, 50, 800, 5, 13, 5, 0, 0);
+
+static const struct panel_desc nlt_nl12880bc20_jeida = {
+	.modes = &nlt_nl12880bc20_mode,
+	.num_modes = 1,
+	.bpc = 8,
+	.size = {
+		.width = 261,
+		.height = 163,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
+};
+
+static const struct panel_desc nlt_nl12880bc20_spwg_18 = {
+	.modes = &nlt_nl12880bc20_mode,
+	.num_modes = 1,
+	.bpc = 6,
+	.size = {
+		.width = 261,
+		.height = 163,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+};
+
+static const struct panel_desc nlt_nl12880bc20_spwg_24 = {
+	.modes = &nlt_nl12880bc20_mode,
+	.num_modes = 1,
+	.bpc = 8,
+	.size = {
+		.width = 261,
+		.height = 163,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+};
+
 static const struct drm_display_mode nvd_9128_mode =
 	SP_DISPLAY_MODE(29500, 800, 130, 98, 0, 480, 10, 50, 0, 0, 0);
 
@@ -1707,6 +1743,15 @@ static const struct of_device_id platform_of_match[] = {
 		.compatible = "nlt,nl192108ac18-02d",
 		.data = &nlt_nl192108ac18_02d,
 	}, {
+		.compatible = "nlt,nl12880bc20-jeida",
+		.data = &nlt_nl12880bc20_jeida,
+	}, {
+		.compatible = "nlt,nl12880bc20-spwg-18",
+		.data = &nlt_nl12880bc20_spwg_18,
+	}, {
+		.compatible = "nlt,nl12880bc20-spwg-24",
+		.data = &nlt_nl12880bc20_spwg_24,
+	}, {
 		.compatible = "nvd,9128",
 		.data = &nvd_9128,
 	}, {
-- 
2.1.4

[PATCH 8/9] drm/panel: simple: add support for EDT ETM0700G0EDH6 7" WVGA panel

[Lothar Waßmann]

This panel is the same as ETM0700g0DH6 with an inverted pixel clock.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
---
 .../bindings/display/panel/edt,etm0700g0edh6.txt          |  9 +++++++++
 drivers/gpu/drm/panel/panel-simple.c                      | 15 +++++++++++++++
 2 files changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0edh6.txt

diff --git a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0edh6.txt b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0edh6.txt
new file mode 100644
index 0000000..e6e8ef5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0edh6.txt
@@ -0,0 +1,9 @@
+Emerging Display Technology Corp. ETM0700G0EDH6 7.0" WVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "edt,etm0700g0edh6"
+
+This panel is the same as ETM0700g0DH6 with and inverted pixel clock.
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 52e0cb6..d4d2a89 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -827,6 +827,18 @@ static const struct panel_desc edt_etm0700g0dh6 = {
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
 };
 
+static const struct panel_desc edt_etm0700g0edh6 = {
+	.modes = &edt_etm0700g0dh6_mode,
+	.num_modes = 1,
+	.bpc = 6,
+	.size = {
+		.width = 152,
+		.height = 91,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
+};
+
 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode =
 	SP_DISPLAY_MODE(32260, 800, 168, 64, 88, 480, 37, 2, 8, 60, 0);
 
@@ -1674,6 +1686,9 @@ static const struct of_device_id platform_of_match[] = {
 		.compatible = "edt,etm0700g0dh6",
 		.data = &edt_etm0700g0dh6,
 	}, {
+		.compatible = "edt,etm0700g0edh6",
+		.data = &edt_etm0700g0edh6,
+	}, {
 		.compatible = "foxlink,fl500wvr00-a0t",
 		.data = &foxlink_fl500wvr00_a0t,
 	}, {
-- 
2.1.4

[PATCH 9/9] drm/panel: simple: add support for EDT ET1010G0DSA/ETML1010G0DKA 10.1" WXGA LVDS panels

[Lothar Waßmann]

This adds support for the Emerging Display Technologies Corporation
10.1" WXGA LVDS panel ET1010G0DSA (without a touch panel) and
ETML1010G0DKA (with capacitive touch panel).

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
---
 .../bindings/display/panel/edt,et1010g0dsa.txt     |  7 +++++++
 .../bindings/display/panel/edt,etml1010g0dka.txt   |  9 +++++++++
 drivers/gpu/drm/panel/panel-simple.c               | 22 ++++++++++++++++++++++
 3 files changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et1010g0dsa.txt
 create mode 100644 Documentation/devicetree/bindings/display/panel/edt,etml1010g0dka.txt

diff --git a/Documentation/devicetree/bindings/display/panel/edt,et1010g0dsa.txt b/Documentation/devicetree/bindings/display/panel/edt,et1010g0dsa.txt
new file mode 100644
index 0000000..f76e070
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/edt,et1010g0dsa.txt
@@ -0,0 +1,7 @@
+Emerging Display Technology Corp. ET1010G0DSA 10.1" WXGA TFT LVDS display panel
+
+Required properties:
+- compatible: should be "edt,et1010g0dsa"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/edt,etml1010g0dka.txt b/Documentation/devicetree/bindings/display/panel/edt,etml1010g0dka.txt
new file mode 100644
index 0000000..1413ea9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/edt,etml1010g0dka.txt
@@ -0,0 +1,9 @@
+Emerging Display Technology Corp. ETML1010G0DKA 10.1" WXGA TFT LVDS display panel
+
+Required properties:
+- compatible: should be "edt,etml1010g0dka"
+
+This panel is the same as ET101G0DSA with an integrated capacitive multitouch panel.
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index d4d2a89..5154cb9 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -839,6 +839,22 @@ static const struct panel_desc edt_etm0700g0edh6 = {
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
 };
 
+static const struct drm_display_mode edt_et1010g0dsa_mode =
+	SP_DISPLAY_MODE(71100, 1280, 25, 80, 55, 800, 5, 2, 16, 60,
+			DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
+
+static const struct panel_desc edt_et1010g0dsa = {
+	.modes = &edt_et1010g0dsa_mode,
+	.num_modes = 1,
+	.bpc = 8,
+	.size = {
+		.width = 217,
+		.height = 136,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
+};
+
 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode =
 	SP_DISPLAY_MODE(32260, 800, 168, 64, 88, 480, 37, 2, 8, 60, 0);
 
@@ -1683,6 +1699,12 @@ static const struct of_device_id platform_of_match[] = {
 		.compatible = "edt,et070080dh6",
 		.data = &edt_etm0700g0dh6,
 	}, {
+		.compatible = "edt,et1010g0dsa",
+		.data = &edt_et1010g0dsa,
+	}, {
+		.compatible = "edt,etml1010g0dka",
+		.data = &edt_et1010g0dsa,
+	}, {
 		.compatible = "edt,etm0700g0dh6",
 		.data = &edt_etm0700g0dh6,
 	}, {
-- 
2.1.4

Re: [PATCH 3/9] drm/panel: simple: make it possible to override LCD bus format

[Rob Herring]

On Wed, Oct 11, 2017 at 01:23:35PM +0200, Lothar Waßmann wrote:
> The baseboards for the Ka-Ro electronics series of i.MX modules
> use a 24bit LCD interface, no matter what LCD bus width the SoC on the
> module provides and what the LCD panel expects. LCDs with 6bit per color
> will ignore the 2 LSBs of each color lane, and modules using a SoC
> that provides only 6bit per color, drive the display information on the
> 6 MSBs of each color lane and tie the 2 LSBs of each color lane to GND.
> 
> Thus, no matter what combination of LCD and SoC is used, the LCD port
> can be used without shuffling bit lanes by always configuring the LCD
> output to 24bit mode.

Thanks for providing good reasoning as to why this is needed.

> 
> Add a function to handle certain quirks of the LCD interface to the
> panel driver to be able to override the bus format specified in a
> panel's display_mode.
> 
> Signed-off-by: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
> ---
>  .../bindings/display/panel/simple-panel.txt        |  2 ++
>  drivers/gpu/drm/panel/panel-simple.c               | 40 +++++++++++++++++++++-
>  2 files changed, 41 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/panel/simple-panel.txt b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
> index 1341bbf..e2308c3 100644
> --- a/Documentation/devicetree/bindings/display/panel/simple-panel.txt
> +++ b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
> @@ -7,6 +7,8 @@ Optional properties:
>  - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
>  - enable-gpios: GPIO pin to enable or disable the panel
>  - backlight: phandle of the backlight device attached to the panel
> +- bus-format-override: override the bus_format setting of the panel's
> +  display_mode settings

You need to define valid values here.

However, we also have this proposal[1]. Please align to a common one. 
BTW, we don't need another common panel binding file that [1] added. We 
already have panel-dpi.txt for parallel interface panels. And 
personally, I'd like to see simple-panel.txt disappear.

Rob

[1] https://patchwork.ozlabs.org/patch/823104/
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Re: [PATCH 4/9] drm/panel: simple: add support for overriding the pixel clock polarity

[Rob Herring]

On Wed, Oct 11, 2017 at 6:23 AM, Lothar Waßmann <LW@karo-electronics.de> wrote:
> The Ka-Ro electronics MB7 baseboard has an on-board LCD->LVDS
> converter that requires a fixed pixelclk polarity, no matter what the
> panel's display_mode specifies. Add an option to override the pixelclk
> polarity defined in the panel's display_mode via DTB.

Wouldn't you know the polarity required based on the type of LVDS
converter chip in front of the panel? Or is that not being described
because it is "transparent".

Rob
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Re: [PATCH 4/9] drm/panel: simple: add support for overriding the pixel clock polarity

[Lothar Waßmann]

Hi,

On Mon, 16 Oct 2017 17:13:29 -0500 Rob Herring wrote:
> On Wed, Oct 11, 2017 at 6:23 AM, Lothar Waßmann <LW-AvR2QvxeiV7DiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org> wrote:
> > The Ka-Ro electronics MB7 baseboard has an on-board LCD->LVDS
> > converter that requires a fixed pixelclk polarity, no matter what the
> > panel's display_mode specifies. Add an option to override the pixelclk
> > polarity defined in the panel's display_mode via DTB.
> 
> Wouldn't you know the polarity required based on the type of LVDS
> converter chip in front of the panel? Or is that not being described
> because it is "transparent".
> 
Exactly the latter.


Lothar Waßmann
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Re: [PATCH 1/9] drm/panel: simple: add a macro for defining display modes in a simpler and less error prone way

[Thierry Reding]

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On Wed, Oct 11, 2017 at 01:23:33PM +0200, Lothar Waßmann wrote:
> Create a macro that eases the definition of display mode parameters by
> accecpting the parameters:
> freq, hactive, hfront-porch, hsynclen, hback-porch,
> vactive, vfront-porch, vsynclen, vback-porch, vrefresh
> that can be usually directly taken from an LCD datasheet.
> 
> Put the calculations that are now open coded repeating the same
> parameters multiple times into the macro expansion.
> 
> Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
> ---
>  drivers/gpu/drm/panel/panel-simple.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index 474fa75..dec639d 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -411,6 +411,20 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
>  	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
>  };
>  
> +#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> +	.clock = freq,							\
> +	.hdisplay = ha,							\
> +	.hsync_start = (ha) + (hfp),					\
> +	.hsync_end = (ha) + (hfp) + (hs),				\
> +	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> +	.vdisplay = (va),						\
> +	.vsync_start = (va) + (vfp),					\
> +	.vsync_end = (va) + (vfp) + (vs),				\
> +	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> +	.vrefresh = vr,							\
> +	.flags = flgs,							\
> +	}

I don't think this simplifies anything. It's now completely non-obvious
which parameter is which, so you actually have to go look at the macro
definition when you add a new mode to make sure you get them right.

Thierry

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Re: [PATCH 2/9] drm/panel: simple: simplify display_mode definitions by using macro

[Thierry Reding]

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On Wed, Oct 11, 2017 at 01:23:34PM +0200, Lothar Waßmann wrote:
> Use the newly defined macro to generate the display_mode data entries
> for all panels. This reduces the code size significantly and makes the
> code more readable.
> 
> Signed-off-by: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
> ---
>  drivers/gpu/drm/panel/panel-simple.c | 799 ++++++-----------------------------
>  1 file changed, 134 insertions(+), 665 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index dec639d..fde9c41 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -89,6 +89,20 @@ struct panel_simple {
>  	struct gpio_desc *enable_gpio;
>  };
>  
> +#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> +	.clock = freq,							\
> +	.hdisplay = ha,							\
> +	.hsync_start = (ha) + (hfp),					\
> +	.hsync_end = (ha) + (hfp) + (hs),				\
> +	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> +	.vdisplay = (va),						\
> +	.vsync_start = (va) + (vfp),					\
> +	.vsync_end = (va) + (vfp) + (vs),				\
> +	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> +	.vrefresh = vr,							\
> +	.flags = flgs,							\
> +}
> +
>  static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
>  {
>  	return container_of(panel, struct panel_simple, base);
[...]
> @@ -411,33 +415,9 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
>  	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
>  };
>  
> -#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> -	.clock = freq,							\
> -	.hdisplay = ha,							\
> -	.hsync_start = (ha) + (hfp),					\
> -	.hsync_end = (ha) + (hfp) + (hs),				\
> -	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> -	.vdisplay = (va),						\
> -	.vsync_start = (va) + (vfp),					\
> -	.vsync_end = (va) + (vfp) + (vs),				\
> -	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> -	.vrefresh = vr,							\
> -	.flags = flgs,							\
> -	}

Your first patch should put this in the right place to begin with so
that this patch is really just the conversion.

Again, I don't think this macro actually improves the way modes are
defined.

Thierry

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Re: [PATCH 3/9] drm/panel: simple: make it possible to override LCD bus format

[Thierry Reding]

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On Wed, Oct 11, 2017 at 01:23:35PM +0200, Lothar Waßmann wrote:
> The baseboards for the Ka-Ro electronics series of i.MX modules
> use a 24bit LCD interface, no matter what LCD bus width the SoC on the
> module provides and what the LCD panel expects. LCDs with 6bit per color
> will ignore the 2 LSBs of each color lane, and modules using a SoC
> that provides only 6bit per color, drive the display information on the
> 6 MSBs of each color lane and tie the 2 LSBs of each color lane to GND.
> 
> Thus, no matter what combination of LCD and SoC is used, the LCD port
> can be used without shuffling bit lanes by always configuring the LCD
> output to 24bit mode.
> 
> Add a function to handle certain quirks of the LCD interface to the
> panel driver to be able to override the bus format specified in a
> panel's display_mode.

I think the above paragraph clearly indicates that this is the wrong
place to workaround this. You say yourself that the LCD interface has
quirks that need to be handled, so why do you want to force this
handling into the panel driver?

The panel remains the same, no matter what interface you connect it to.

Thierry

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Re: [PATCH 1/9] drm/panel: simple: add a macro for defining display modes in a simpler and less error prone way

[Lothar Waßmann]

Hi,

On Tue, 17 Oct 2017 14:08:18 +0200 Thierry Reding wrote:
> On Wed, Oct 11, 2017 at 01:23:33PM +0200, Lothar Waßmann wrote:
> > Create a macro that eases the definition of display mode parameters by
> > accecpting the parameters:
> > freq, hactive, hfront-porch, hsynclen, hback-porch,
> > vactive, vfront-porch, vsynclen, vback-porch, vrefresh
> > that can be usually directly taken from an LCD datasheet.
> > 
> > Put the calculations that are now open coded repeating the same
> > parameters multiple times into the macro expansion.
> > 
> > Signed-off-by: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
> > ---
> >  drivers/gpu/drm/panel/panel-simple.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > index 474fa75..dec639d 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -411,6 +411,20 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
> >  	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> >  };
> >  
> > +#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> > +	.clock = freq,							\
> > +	.hdisplay = ha,							\
> > +	.hsync_start = (ha) + (hfp),					\
> > +	.hsync_end = (ha) + (hfp) + (hs),				\
> > +	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> > +	.vdisplay = (va),						\
> > +	.vsync_start = (va) + (vfp),					\
> > +	.vsync_end = (va) + (vfp) + (vs),				\
> > +	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> > +	.vrefresh = vr,							\
> > +	.flags = flgs,							\
> > +	}
> 
> I don't think this simplifies anything. It's now completely non-obvious
> which parameter is which, so you actually have to go look at the macro
> definition when you add a new mode to make sure you get them right.
> 
In the original code you have to repeat the same parameters (e.g.
vertical front porch (vfp)) in multiple places which is error prone.


Lothar Waßmann
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Re: [PATCH 4/9] drm/panel: simple: add support for overriding the pixel clock polarity

[Thierry Reding]

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On Wed, Oct 11, 2017 at 01:23:36PM +0200, Lothar Waßmann wrote:
> The Ka-Ro electronics MB7 baseboard has an on-board LCD->LVDS
> converter that requires a fixed pixelclk polarity, no matter what the
> panel's display_mode specifies. Add an option to override the pixelclk
> polarity defined in the panel's display_mode via DTB.

I'd argue that the LCD->LVDS converter should be modelled specifically
in DT to handle this case. It could be a implemented as a DRM bridge
driver, for example.

Thierry

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Re: [PATCH 4/9] drm/panel: simple: add support for overriding the pixel clock polarity

[Lothar Waßmann]

Hi,

On Tue, 17 Oct 2017 14:14:22 +0200 Thierry Reding wrote:
> On Wed, Oct 11, 2017 at 01:23:36PM +0200, Lothar Waßmann wrote:
> > The Ka-Ro electronics MB7 baseboard has an on-board LCD->LVDS
> > converter that requires a fixed pixelclk polarity, no matter what the
> > panel's display_mode specifies. Add an option to override the pixelclk
> > polarity defined in the panel's display_mode via DTB.
> 
> I'd argue that the LCD->LVDS converter should be modelled specifically
> in DT to handle this case. It could be a implemented as a DRM bridge
> driver, for example.
> 
IMO that's just overkill for a simple chip that is in no way
configurable nor detectable by software.


Lothar Waßmann

Re: [PATCH 3/9] drm/panel: simple: make it possible to override LCD bus format

[Lothar Waßmann]

Hi,

On Tue, 17 Oct 2017 14:12:40 +0200 Thierry Reding wrote:
> On Wed, Oct 11, 2017 at 01:23:35PM +0200, Lothar Waßmann wrote:
> > The baseboards for the Ka-Ro electronics series of i.MX modules
> > use a 24bit LCD interface, no matter what LCD bus width the SoC on the
> > module provides and what the LCD panel expects. LCDs with 6bit per color
> > will ignore the 2 LSBs of each color lane, and modules using a SoC
> > that provides only 6bit per color, drive the display information on the
> > 6 MSBs of each color lane and tie the 2 LSBs of each color lane to GND.
> > 
> > Thus, no matter what combination of LCD and SoC is used, the LCD port
> > can be used without shuffling bit lanes by always configuring the LCD
> > output to 24bit mode.
> > 
> > Add a function to handle certain quirks of the LCD interface to the
> > panel driver to be able to override the bus format specified in a
> > panel's display_mode.
> 
> I think the above paragraph clearly indicates that this is the wrong
> place to workaround this. You say yourself that the LCD interface has
> quirks that need to be handled, so why do you want to force this
> handling into the panel driver?
> 
The quirk is in the interfacing of the SoM's LCD output to the LCD
panel. Thus it can be handled in either place.

> The panel remains the same, no matter what interface you connect it to.
> 
Because that's just ONE place to change, no matter what LCD driver is
being used.


Lothar Waßmann
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Re: [PATCH 4/9] drm/panel: simple: add support for overriding the pixel clock polarity

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 1103 bytes --]

On Tue, Oct 17, 2017 at 02:25:07PM +0200, Lothar Waßmann wrote:
> Hi,
> 
> On Tue, 17 Oct 2017 14:14:22 +0200 Thierry Reding wrote:
> > On Wed, Oct 11, 2017 at 01:23:36PM +0200, Lothar Waßmann wrote:
> > > The Ka-Ro electronics MB7 baseboard has an on-board LCD->LVDS
> > > converter that requires a fixed pixelclk polarity, no matter what the
> > > panel's display_mode specifies. Add an option to override the pixelclk
> > > polarity defined in the panel's display_mode via DTB.
> > 
> > I'd argue that the LCD->LVDS converter should be modelled specifically
> > in DT to handle this case. It could be a implemented as a DRM bridge
> > driver, for example.
> > 
> IMO that's just overkill for a simple chip that is in no way
> configurable nor detectable by software.

I suspect that you're not the only one who runs a board that has this
kind of quirk. If we solve this in a generic way we can point people in
that direction when they come asking for such a quirk.

So this could be something very simple that's instantiated using maybe a
couple of lines of code.

Thierry

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Re: [PATCH 1/9] drm/panel: simple: add a macro for defining display modes in a simpler and less error prone way

[Thierry Reding]

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On Tue, Oct 17, 2017 at 02:13:37PM +0200, Lothar Waßmann wrote:
> Hi,
> 
> On Tue, 17 Oct 2017 14:08:18 +0200 Thierry Reding wrote:
> > On Wed, Oct 11, 2017 at 01:23:33PM +0200, Lothar Waßmann wrote:
> > > Create a macro that eases the definition of display mode parameters by
> > > accecpting the parameters:
> > > freq, hactive, hfront-porch, hsynclen, hback-porch,
> > > vactive, vfront-porch, vsynclen, vback-porch, vrefresh
> > > that can be usually directly taken from an LCD datasheet.
> > > 
> > > Put the calculations that are now open coded repeating the same
> > > parameters multiple times into the macro expansion.
> > > 
> > > Signed-off-by: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
> > > ---
> > >  drivers/gpu/drm/panel/panel-simple.c | 14 ++++++++++++++
> > >  1 file changed, 14 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > > index 474fa75..dec639d 100644
> > > --- a/drivers/gpu/drm/panel/panel-simple.c
> > > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > > @@ -411,6 +411,20 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
> > >  	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> > >  };
> > >  
> > > +#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> > > +	.clock = freq,							\
> > > +	.hdisplay = ha,							\
> > > +	.hsync_start = (ha) + (hfp),					\
> > > +	.hsync_end = (ha) + (hfp) + (hs),				\
> > > +	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> > > +	.vdisplay = (va),						\
> > > +	.vsync_start = (va) + (vfp),					\
> > > +	.vsync_end = (va) + (vfp) + (vs),				\
> > > +	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> > > +	.vrefresh = vr,							\
> > > +	.flags = flgs,							\
> > > +	}
> > 
> > I don't think this simplifies anything. It's now completely non-obvious
> > which parameter is which, so you actually have to go look at the macro
> > definition when you add a new mode to make sure you get them right.
> > 
> In the original code you have to repeat the same parameters (e.g.
> vertical front porch (vfp)) in multiple places which is error prone.

I don't think this is an issue. The definitions initialize the fields in
the natural order, so the repetitions are where very localized and quite
difficult to actually get wrong. I've never seen anyone get it wrong for
any panel.

Also note that the above notation is only out of convenience to make it
clearer what the active, front-porch, sync and back-porch values are.
You can easily just collapse them into the sum if you're worried about
the repetition.

Alternatively, are you aware of struct display_timing? It's a different
way to describe the timings which doesn't require repeating the values.
simple-panel already supports those as an alternative to the struct
drm_display_mode.

Thierry

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Re: [PATCH 3/9] drm/panel: simple: make it possible to override LCD bus format

[Thierry Reding]

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On Tue, Oct 17, 2017 at 02:44:23PM +0200, Lothar Waßmann wrote:
> Hi,
> 
> On Tue, 17 Oct 2017 14:12:40 +0200 Thierry Reding wrote:
> > On Wed, Oct 11, 2017 at 01:23:35PM +0200, Lothar Waßmann wrote:
> > > The baseboards for the Ka-Ro electronics series of i.MX modules
> > > use a 24bit LCD interface, no matter what LCD bus width the SoC on the
> > > module provides and what the LCD panel expects. LCDs with 6bit per color
> > > will ignore the 2 LSBs of each color lane, and modules using a SoC
> > > that provides only 6bit per color, drive the display information on the
> > > 6 MSBs of each color lane and tie the 2 LSBs of each color lane to GND.
> > > 
> > > Thus, no matter what combination of LCD and SoC is used, the LCD port
> > > can be used without shuffling bit lanes by always configuring the LCD
> > > output to 24bit mode.
> > > 
> > > Add a function to handle certain quirks of the LCD interface to the
> > > panel driver to be able to override the bus format specified in a
> > > panel's display_mode.
> > 
> > I think the above paragraph clearly indicates that this is the wrong
> > place to workaround this. You say yourself that the LCD interface has
> > quirks that need to be handled, so why do you want to force this
> > handling into the panel driver?
> > 
> The quirk is in the interfacing of the SoM's LCD output to the LCD
> panel. Thus it can be handled in either place.

Yes. What I'm saying is that the panel is, in my opinion, the wrong
place to handle an LCD interface (originating from the SoM) quirk.

> > The panel remains the same, no matter what interface you connect it to.
> > 
> Because that's just ONE place to change, no matter what LCD driver is
> being used.

That's a Linux specific implementation detail. If you ever want to use
a panel that is not driven by simple-panel you'd have to change it in
that driver, too.

Thierry

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Re: [PATCH 2/9] drm/panel: simple: simplify display_mode definitions by using macro

[Lothar Waßmann]

Hi,

On Tue, 17 Oct 2017 14:09:37 +0200 Thierry Reding wrote:
> On Wed, Oct 11, 2017 at 01:23:34PM +0200, Lothar Waßmann wrote:
> > Use the newly defined macro to generate the display_mode data entries
> > for all panels. This reduces the code size significantly and makes the
> > code more readable.
> > 
> > Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
> > ---
> >  drivers/gpu/drm/panel/panel-simple.c | 799 ++++++-----------------------------
> >  1 file changed, 134 insertions(+), 665 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > index dec639d..fde9c41 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -89,6 +89,20 @@ struct panel_simple {
> >  	struct gpio_desc *enable_gpio;
> >  };
> >  
> > +#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> > +	.clock = freq,							\
> > +	.hdisplay = ha,							\
> > +	.hsync_start = (ha) + (hfp),					\
> > +	.hsync_end = (ha) + (hfp) + (hs),				\
> > +	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> > +	.vdisplay = (va),						\
> > +	.vsync_start = (va) + (vfp),					\
> > +	.vsync_end = (va) + (vfp) + (vs),				\
> > +	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> > +	.vrefresh = vr,							\
> > +	.flags = flgs,							\
> > +}
> > +
> >  static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
> >  {
> >  	return container_of(panel, struct panel_simple, base);
> [...]
> > @@ -411,33 +415,9 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
> >  	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> >  };
> >  
> > -#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> > -	.clock = freq,							\
> > -	.hdisplay = ha,							\
> > -	.hsync_start = (ha) + (hfp),					\
> > -	.hsync_end = (ha) + (hfp) + (hs),				\
> > -	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> > -	.vdisplay = (va),						\
> > -	.vsync_start = (va) + (vfp),					\
> > -	.vsync_end = (va) + (vfp) + (vs),				\
> > -	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> > -	.vrefresh = vr,							\
> > -	.flags = flgs,							\
> > -	}
> 
> Your first patch should put this in the right place to begin with so
> that this patch is really just the conversion.
> 
> Again, I don't think this macro actually improves the way modes are
> defined.
> 
I'm not happy with this panel driver stuff anyway. With the legacy
'display-timings' node that provided the timing data directly in the
DTB, every bootloader could pick up the timing data and feed it to
whatever driver it used for the display.
With the panel driver stuff the whole Linux driver has to be replicated
in the boot loader in order to be able to use the same DTB as Linux for
its HW configuration.
And adding a new panel involves recompiling the kernel and the boot
loader, rather than adding the timing data from the panel's datasheet
into the DTB.


Lothar Waßmann

Re: [PATCH 2/9] drm/panel: simple: simplify display_mode definitions by using macro

[Thierry Reding]

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On Tue, Oct 17, 2017 at 03:05:16PM +0200, Lothar Waßmann wrote:
> Hi,
> 
> On Tue, 17 Oct 2017 14:09:37 +0200 Thierry Reding wrote:
> > On Wed, Oct 11, 2017 at 01:23:34PM +0200, Lothar Waßmann wrote:
> > > Use the newly defined macro to generate the display_mode data entries
> > > for all panels. This reduces the code size significantly and makes the
> > > code more readable.
> > > 
> > > Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
> > > ---
> > >  drivers/gpu/drm/panel/panel-simple.c | 799 ++++++-----------------------------
> > >  1 file changed, 134 insertions(+), 665 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > > index dec639d..fde9c41 100644
> > > --- a/drivers/gpu/drm/panel/panel-simple.c
> > > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > > @@ -89,6 +89,20 @@ struct panel_simple {
> > >  	struct gpio_desc *enable_gpio;
> > >  };
> > >  
> > > +#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> > > +	.clock = freq,							\
> > > +	.hdisplay = ha,							\
> > > +	.hsync_start = (ha) + (hfp),					\
> > > +	.hsync_end = (ha) + (hfp) + (hs),				\
> > > +	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> > > +	.vdisplay = (va),						\
> > > +	.vsync_start = (va) + (vfp),					\
> > > +	.vsync_end = (va) + (vfp) + (vs),				\
> > > +	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> > > +	.vrefresh = vr,							\
> > > +	.flags = flgs,							\
> > > +}
> > > +
> > >  static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
> > >  {
> > >  	return container_of(panel, struct panel_simple, base);
> > [...]
> > > @@ -411,33 +415,9 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
> > >  	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> > >  };
> > >  
> > > -#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> > > -	.clock = freq,							\
> > > -	.hdisplay = ha,							\
> > > -	.hsync_start = (ha) + (hfp),					\
> > > -	.hsync_end = (ha) + (hfp) + (hs),				\
> > > -	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> > > -	.vdisplay = (va),						\
> > > -	.vsync_start = (va) + (vfp),					\
> > > -	.vsync_end = (va) + (vfp) + (vs),				\
> > > -	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> > > -	.vrefresh = vr,							\
> > > -	.flags = flgs,							\
> > > -	}
> > 
> > Your first patch should put this in the right place to begin with so
> > that this patch is really just the conversion.
> > 
> > Again, I don't think this macro actually improves the way modes are
> > defined.
> > 
> I'm not happy with this panel driver stuff anyway. With the legacy
> 'display-timings' node that provided the timing data directly in the
> DTB, every bootloader could pick up the timing data and feed it to
> whatever driver it used for the display.
> With the panel driver stuff the whole Linux driver has to be replicated
> in the boot loader in order to be able to use the same DTB as Linux for
> its HW configuration.
> And adding a new panel involves recompiling the kernel and the boot
> loader, rather than adding the timing data from the panel's datasheet
> into the DTB.

This isn't the first time I've heard this. Please read this for more
background information on why the situation is what it is:

	http://sietch-tagr.blogspot.de/2016/04/display-panels-are-not-special.html

Thierry

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Re: [PATCH 2/9] drm/panel: simple: simplify display_mode definitions by using macro

[Lothar Waßmann]

Hi,

On Tue, 17 Oct 2017 15:08:31 +0200 Thierry Reding wrote:
> On Tue, Oct 17, 2017 at 03:05:16PM +0200, Lothar Waßmann wrote:
> > Hi,
> > 
> > On Tue, 17 Oct 2017 14:09:37 +0200 Thierry Reding wrote:
> > > On Wed, Oct 11, 2017 at 01:23:34PM +0200, Lothar Waßmann wrote:
> > > > Use the newly defined macro to generate the display_mode data entries
> > > > for all panels. This reduces the code size significantly and makes the
> > > > code more readable.
> > > > 
> > > > Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
> > > > ---
> > > >  drivers/gpu/drm/panel/panel-simple.c | 799 ++++++-----------------------------
> > > >  1 file changed, 134 insertions(+), 665 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > > > index dec639d..fde9c41 100644
> > > > --- a/drivers/gpu/drm/panel/panel-simple.c
> > > > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > > > @@ -89,6 +89,20 @@ struct panel_simple {
> > > >  	struct gpio_desc *enable_gpio;
> > > >  };
> > > >  
> > > > +#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> > > > +	.clock = freq,							\
> > > > +	.hdisplay = ha,							\
> > > > +	.hsync_start = (ha) + (hfp),					\
> > > > +	.hsync_end = (ha) + (hfp) + (hs),				\
> > > > +	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> > > > +	.vdisplay = (va),						\
> > > > +	.vsync_start = (va) + (vfp),					\
> > > > +	.vsync_end = (va) + (vfp) + (vs),				\
> > > > +	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> > > > +	.vrefresh = vr,							\
> > > > +	.flags = flgs,							\
> > > > +}
> > > > +
> > > >  static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
> > > >  {
> > > >  	return container_of(panel, struct panel_simple, base);
> > > [...]
> > > > @@ -411,33 +415,9 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
> > > >  	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> > > >  };
> > > >  
> > > > -#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
> > > > -	.clock = freq,							\
> > > > -	.hdisplay = ha,							\
> > > > -	.hsync_start = (ha) + (hfp),					\
> > > > -	.hsync_end = (ha) + (hfp) + (hs),				\
> > > > -	.htotal = (ha) + (hfp) + (hs) + (hbp),				\
> > > > -	.vdisplay = (va),						\
> > > > -	.vsync_start = (va) + (vfp),					\
> > > > -	.vsync_end = (va) + (vfp) + (vs),				\
> > > > -	.vtotal = (va) + (vfp) + (vs) + (vbp),				\
> > > > -	.vrefresh = vr,							\
> > > > -	.flags = flgs,							\
> > > > -	}
> > > 
> > > Your first patch should put this in the right place to begin with so
> > > that this patch is really just the conversion.
> > > 
> > > Again, I don't think this macro actually improves the way modes are
> > > defined.
> > > 
> > I'm not happy with this panel driver stuff anyway. With the legacy
> > 'display-timings' node that provided the timing data directly in the
> > DTB, every bootloader could pick up the timing data and feed it to
> > whatever driver it used for the display.
> > With the panel driver stuff the whole Linux driver has to be replicated
> > in the boot loader in order to be able to use the same DTB as Linux for
> > its HW configuration.
> > And adding a new panel involves recompiling the kernel and the boot
> > loader, rather than adding the timing data from the panel's datasheet
> > into the DTB.
> 
> This isn't the first time I've heard this. Please read this for more
> background information on why the situation is what it is:
> 
> 	http://sietch-tagr.blogspot.de/2016/04/display-panels-are-not-special.html
> 
Thanks for the link. That's what I have been looking for already for
some time but couldn't find any references to.


Lothar Waßmann

Re: [PATCH 3/9] drm/panel: simple: make it possible to override LCD bus format

[Rob Herring]

On Tue, Oct 17, 2017 at 7:56 AM, Thierry Reding
<thierry.reding@gmail.com> wrote:
> On Tue, Oct 17, 2017 at 02:44:23PM +0200, Lothar Waßmann wrote:
>> Hi,
>>
>> On Tue, 17 Oct 2017 14:12:40 +0200 Thierry Reding wrote:
>> > On Wed, Oct 11, 2017 at 01:23:35PM +0200, Lothar Waßmann wrote:
>> > > The baseboards for the Ka-Ro electronics series of i.MX modules
>> > > use a 24bit LCD interface, no matter what LCD bus width the SoC on the
>> > > module provides and what the LCD panel expects. LCDs with 6bit per color
>> > > will ignore the 2 LSBs of each color lane, and modules using a SoC
>> > > that provides only 6bit per color, drive the display information on the
>> > > 6 MSBs of each color lane and tie the 2 LSBs of each color lane to GND.
>> > >
>> > > Thus, no matter what combination of LCD and SoC is used, the LCD port
>> > > can be used without shuffling bit lanes by always configuring the LCD
>> > > output to 24bit mode.
>> > >
>> > > Add a function to handle certain quirks of the LCD interface to the
>> > > panel driver to be able to override the bus format specified in a
>> > > panel's display_mode.
>> >
>> > I think the above paragraph clearly indicates that this is the wrong
>> > place to workaround this. You say yourself that the LCD interface has
>> > quirks that need to be handled, so why do you want to force this
>> > handling into the panel driver?
>> >
>> The quirk is in the interfacing of the SoM's LCD output to the LCD
>> panel. Thus it can be handled in either place.
>
> Yes. What I'm saying is that the panel is, in my opinion, the wrong
> place to handle an LCD interface (originating from the SoM) quirk.

There's 2 possible things we could need to describe here. First, is
any restrictions the SoM has. For example, the SoM has an 18-bit
interface while the SoC has a 24-bit interface. Second, is how a panel
with fewer bits than the interface (whether a SoM or direct to SoC) is
wired up. If we think about this in terms of a base DT plus overlays,
then the former case belongs in the base and the latter belongs in the
overlay. If the SoM interface needs to be SoC independent, then it
gets more complicated as we don't want to have the SoC's LCD
controller node in the overlay adding properties to it and therefore
need to have some sort of translation (i.e. a connector binding). But
we have no definition of how we would describe OF graph thru a
connector.

In the end, these are board level properties, so you can make the same
argument that this property doesn't belong in the SoC's LCD controller
node as you can it doesn't belong in the panel node. Generally, we
just default to the node bound to the driver we want to handle the
property.

In any case, I think this should be properties of the endpoints rather
than the endpoint parent nodes as it is a property of the interface,
not the controller nor the panel. This is also how camera interfaces
were done. An LCD controller node could have 2 interfaces for example.

>> > The panel remains the same, no matter what interface you connect it to.
>> >
>> Because that's just ONE place to change, no matter what LCD driver is
>> being used.
>
> That's a Linux specific implementation detail. If you ever want to use
> a panel that is not driven by simple-panel you'd have to change it in
> that driver, too.

I do agree the implementation belongs in the LCD controller side, but
just because the property is in the panel node that doesn't mean it's
the panel driver that has to handle the property. As long as the
property is parse-able in a standard way, the "parent" can do it.
There are cases where the driver tied to the parent node handles
properties in the child nodes. SPI timing modes is one example. In
this case, I think we'll need to handle this property being in the
local endpoint and the remote endpoint and resolving the format needed
based on that (as well as what the panel driver says). That's going to
be needed with overlays and connectors anyways and then you don't
really have to care where the restriction comes from.

Rob
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Re: [PATCH 5/9] drm/panel: simple: add support for EDT ET0350 3.5" QVGA panel

[Rob Herring]

On Wed, Oct 11, 2017 at 01:23:37PM +0200, Lothar Waßmann wrote:
> Signed-off-by: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
> ---
>  .../bindings/display/panel/edt,et0350g0dh6.txt        |  7 +++++++

Please split bindings to separate patch.

>  drivers/gpu/drm/panel/panel-simple.c                  | 19 +++++++++++++++++++
>  2 files changed, 26 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et0350g0dh6.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/panel/edt,et0350g0dh6.txt b/Documentation/devicetree/bindings/display/panel/edt,et0350g0dh6.txt
> new file mode 100644
> index 0000000..5546221
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/edt,et0350g0dh6.txt
> @@ -0,0 +1,7 @@
> +Emerging Display Technology Corp. 3.5" QVGA (320x240) TFT LCD panel
> +
> +Required properties:
> +- compatible: should be "edt,et0350g0dh6"
> +
> +This binding is compatible with the simple-panel binding, which is specified
> +in simple-panel.txt in this directory.

No reset lines, power supplies, etc.? Yes, simple-panel.txt defines 
properties, but you still need to specify which ones you use. Otherwise, 
I don't know if this panel has a single supply or you just forgot to 
define the supplies.

Rob
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Re: [PATCH 4/9] drm/panel: simple: add support for overriding the pixel clock polarity

[Lothar Waßmann]

Hi,

On Tue, 17 Oct 2017 14:45:04 +0200 Thierry Reding wrote:
> On Tue, Oct 17, 2017 at 02:25:07PM +0200, Lothar Waßmann wrote:
> > Hi,
> > 
> > On Tue, 17 Oct 2017 14:14:22 +0200 Thierry Reding wrote:
> > > On Wed, Oct 11, 2017 at 01:23:36PM +0200, Lothar Waßmann wrote:
> > > > The Ka-Ro electronics MB7 baseboard has an on-board LCD->LVDS
> > > > converter that requires a fixed pixelclk polarity, no matter what the
> > > > panel's display_mode specifies. Add an option to override the pixelclk
> > > > polarity defined in the panel's display_mode via DTB.
> > > 
> > > I'd argue that the LCD->LVDS converter should be modelled specifically
> > > in DT to handle this case. It could be a implemented as a DRM bridge
> > > driver, for example.
> > > 
> > IMO that's just overkill for a simple chip that is in no way
> > configurable nor detectable by software.
> 
> I suspect that you're not the only one who runs a board that has this
> kind of quirk. If we solve this in a generic way we can point people in
> that direction when they come asking for such a quirk.
> 
> So this could be something very simple that's instantiated using maybe a
> couple of lines of code.
> 
I found the drivers/gpu/drm/bridge/lvds-encoder.c driver which on first
glance is more or less what I would need. But the driver is currently
dysfunctional due to:
|commit 13dfc0540a575b47b2d640b093ac16e9e09474f6
|Author: Eric Anholt <eric@anholt.net>
|Date:   Fri Jun 2 13:25:14 2017 -0700
|
|    drm/bridge: Refactor out the panel wrapper from the lvds-encoder bridge.

Also there is no in-kernel user of this driver, so that it obviously
doesn't get tested in any way.
There is only one dts file (r8a7779-marzen.dts) that instantiate this
driver, but it has an incomplete OF graph. The missing link for the
OF graph is provided by either r8a77xx-aa104xd12-panel.dtsi or
r8a77xx-aa121td01-panel.dtsi, but those files are referenced nowhere in
the kernel source.

Reverting the part of the above mentioned patch that touches
lvds-encoder.c makes the driver functional, but I see no way to use
this driver to enforce specific bus_flags for the interface, since the
code is run prior to the simple-panel's initialization, which would
override whatever settings might have been provided by the lvds-encoder
driver.

Can someone enligthen me, how to enforce specific bus_flags/bus_format
settings for an LCD interface driven by the simple-panel driver apart
from doing it in the simple-panel driver itself?


Lothar Waßmann