From: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
To: Stephen Boyd <sboyd@codeaurora.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
Arnd Bergmann <arnd@arndb.de>, Mark Brown <broonie@kernel.org>,
Xiaolong Zhang <xiaolong.zhang@spreadtrum.com>,
Ben Li <ben.li@spreadtrum.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Orson Zhai <orson.zhai@spreadtrum.com>,
Chunyan Zhang <zhang.lyra@gmail.com>
Subject: [PATCH V3 07/11] clk: sprd: add composite clock support
Date: Thu, 2 Nov 2017 14:56:22 +0800 [thread overview]
Message-ID: <20171102065626.21835-8-chunyan.zhang@spreadtrum.com> (raw)
In-Reply-To: <20171102065626.21835-1-chunyan.zhang@spreadtrum.com>
This patch introduced composite driver for Spreadtrum's SoCs. The
functions of this composite clock simply consist of divider and
mux clocks.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
---
drivers/clk/sprd/Makefile | 1 +
drivers/clk/sprd/composite.c | 65 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/sprd/composite.h | 49 +++++++++++++++++++++++++++++++++
3 files changed, 115 insertions(+)
create mode 100644 drivers/clk/sprd/composite.c
create mode 100644 drivers/clk/sprd/composite.h
diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
index 80e6039..2262e76 100644
--- a/drivers/clk/sprd/Makefile
+++ b/drivers/clk/sprd/Makefile
@@ -4,3 +4,4 @@ clk-sprd-y += common.o
clk-sprd-y += gate.o
clk-sprd-y += mux.o
clk-sprd-y += div.o
+clk-sprd-y += composite.o
diff --git a/drivers/clk/sprd/composite.c b/drivers/clk/sprd/composite.c
new file mode 100644
index 0000000..30d5b36
--- /dev/null
+++ b/drivers/clk/sprd/composite.c
@@ -0,0 +1,65 @@
+/*
+ * Spreadtrum composite clock driver
+ *
+ * Copyright (C) 2017 Spreadtrum, Inc.
+ * Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/clk-provider.h>
+
+#include "composite.h"
+
+DEFINE_SPINLOCK(sprd_comp_lock);
+EXPORT_SYMBOL_GPL(sprd_comp_lock);
+
+static long sprd_comp_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_div_helper_round_rate(&cc->common, &cc->div,
+ rate, parent_rate);
+}
+
+static unsigned long sprd_comp_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_div_helper_recalc_rate(&cc->common, &cc->div, parent_rate);
+}
+
+static int sprd_comp_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_div_helper_set_rate(&cc->common, &cc->div,
+ rate, parent_rate);
+}
+
+static u8 sprd_comp_get_parent(struct clk_hw *hw)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_mux_helper_get_parent(&cc->common, &cc->mux);
+}
+
+static int sprd_comp_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_mux_helper_set_parent(&cc->common, &cc->mux, index);
+}
+
+const struct clk_ops sprd_comp_ops = {
+ .get_parent = sprd_comp_get_parent,
+ .set_parent = sprd_comp_set_parent,
+
+ .round_rate = sprd_comp_round_rate,
+ .recalc_rate = sprd_comp_recalc_rate,
+ .set_rate = sprd_comp_set_rate,
+};
+EXPORT_SYMBOL_GPL(sprd_comp_ops);
diff --git a/drivers/clk/sprd/composite.h b/drivers/clk/sprd/composite.h
new file mode 100644
index 0000000..551f274
--- /dev/null
+++ b/drivers/clk/sprd/composite.h
@@ -0,0 +1,49 @@
+/*
+ * Spreadtrum composite clock driver
+ *
+ * Copyright (C) 2017 Spreadtrum, Inc.
+ * Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _SPRD_COMPOSITE_H_
+#define _SPRD_COMPOSITE_H_
+
+#include "common.h"
+#include "mux.h"
+#include "div.h"
+
+struct sprd_comp {
+ struct sprd_mux_internal mux;
+ struct sprd_div_internal div;
+ struct sprd_clk_common common;
+};
+
+#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _table, \
+ _mshift, _mwidth, _dshift, _dwidth, _flags) \
+ struct sprd_comp _struct = { \
+ .mux = _SPRD_MUX_CLK(_mshift, _mwidth, _table), \
+ .div = _SPRD_DIV_CLK(_dshift, _dwidth), \
+ .common = { \
+ .regmap = NULL, \
+ .reg = _reg, \
+ .lock = &sprd_comp_lock, \
+ .hw.init = CLK_HW_INIT_PARENTS(_name, \
+ _parent, \
+ &sprd_comp_ops, \
+ _flags), \
+ } \
+ }
+
+static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw)
+{
+ struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
+
+ return container_of(common, struct sprd_comp, common);
+}
+
+extern const struct clk_ops sprd_comp_ops;
+extern spinlock_t sprd_comp_lock;
+
+#endif /* _SPRD_COMPOSITE_H_ */
--
2.7.4
next prev parent reply other threads:[~2017-11-02 6:56 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-02 6:56 [PATCH V3 00/11] add clock driver for Spreadtrum platforms Chunyan Zhang
2017-11-02 6:56 ` [PATCH V3 01/11] drivers: move clock common macros out from vendor directories Chunyan Zhang
2017-11-02 6:56 ` [PATCH V3 02/11] dt-bindings: Add Spreadtrum clock binding documentation Chunyan Zhang
[not found] ` <20171102065626.21835-3-chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
2017-11-06 17:15 ` Rob Herring
2017-11-07 7:01 ` Chunyan Zhang
2017-11-02 6:56 ` [PATCH V3 03/11] clk: sprd: Add common infrastructure Chunyan Zhang
2017-11-02 6:56 ` [PATCH V3 04/11] clk: sprd: add gate clock support Chunyan Zhang
2017-11-02 17:45 ` Julien Thierry
2017-11-03 12:12 ` Chunyan Zhang
2017-11-02 6:56 ` [PATCH V3 05/11] clk: sprd: add mux " Chunyan Zhang
2017-11-02 18:11 ` Julien Thierry
2017-11-02 18:22 ` Julien Thierry
2017-11-03 12:12 ` Chunyan Zhang
2017-11-03 12:12 ` Chunyan Zhang
2017-11-02 6:56 ` [PATCH V3 06/11] clk: sprd: add divider " Chunyan Zhang
2017-11-02 6:56 ` Chunyan Zhang [this message]
2017-11-02 6:56 ` [PATCH V3 08/11] clk: sprd: add adjustable pll support Chunyan Zhang
2017-11-02 6:56 ` [PATCH V3 09/11] clk: sprd: add clocks support for SC9860 Chunyan Zhang
2017-11-05 7:59 ` kbuild test robot
2017-11-06 21:43 ` Rob Herring
2017-11-09 8:18 ` Chunyan Zhang
2017-11-10 21:10 ` Rob Herring
2017-11-02 6:56 ` [PATCH V3 10/11] arm64: dts: add syscon for whale2 platform Chunyan Zhang
2017-11-02 6:56 ` [PATCH V3 11/11] arm64: dts: add clocks for SC9860 Chunyan Zhang
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