* [PATCHv4 1/3] ARMv8: dts: ls1046a: add the property of IB and OB
2017-11-10 3:48 [PATCHv4 0/3] dts: Add the property of IB and OB Bao Xiaowei
@ 2017-11-10 3:48 ` Bao Xiaowei
2017-11-10 6:22 ` Kishon Vijay Abraham I
2017-11-10 3:48 ` [PATCHv4 2/3] ARMv8: layerscape: add the pcie ep function support Bao Xiaowei
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Bao Xiaowei @ 2017-11-10 3:48 UTC (permalink / raw)
To: robh+dt, mark.rutland, catalin.marinas, will.deacon, bhelgaas,
shawnguo, madalin.bucur, sumit.garg, yangbo.lu, hongtao.jia,
Yuantian.Tang, leoyang.li, kishon, jingoohan1, pbrobinson,
songxiaowei, devicetree, linux-arm-kernel, linux-kernel,
linux-pci, linuxppc-dev, Zhiqiang.Hou, mingkai.hu, Minghuan.Lian
Cc: Bao Xiaowei
Add the property of inbound and outbound windows number for ep
driver.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
---
v2:
- no change
v3:
- modify the commit message
v4:
- no change
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 06b5e12d04d8..f8332669663c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -674,6 +674,8 @@
device_type = "pci";
dma-coherent;
num-lanes = <4>;
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -699,6 +701,8 @@
device_type = "pci";
dma-coherent;
num-lanes = <2>;
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -724,6 +728,8 @@
device_type = "pci";
dma-coherent;
num-lanes = <2>;
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCHv4 1/3] ARMv8: dts: ls1046a: add the property of IB and OB
2017-11-10 3:48 ` [PATCHv4 1/3] ARMv8: dts: ls1046a: add " Bao Xiaowei
@ 2017-11-10 6:22 ` Kishon Vijay Abraham I
2017-11-10 21:20 ` Leo Li
0 siblings, 1 reply; 12+ messages in thread
From: Kishon Vijay Abraham I @ 2017-11-10 6:22 UTC (permalink / raw)
To: Bao Xiaowei, robh+dt, mark.rutland, catalin.marinas, will.deacon,
bhelgaas, shawnguo, madalin.bucur, sumit.garg, yangbo.lu,
hongtao.jia, Yuantian.Tang, leoyang.li, jingoohan1, pbrobinson,
songxiaowei, devicetree, linux-arm-kernel, linux-kernel,
linux-pci, linuxppc-dev, Zhiqiang.Hou, mingkai.hu, Minghuan.Lian
Hi Bao,
On Friday 10 November 2017 09:18 AM, Bao Xiaowei wrote:
> Add the property of inbound and outbound windows number for ep
> driver.
>
> Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
> ---
> v2:
> - no change
> v3:
> - modify the commit message
> v4:
> - no change
>
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
$subject should start with something like
arm64: dts: ls1046a: **
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index 06b5e12d04d8..f8332669663c 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -674,6 +674,8 @@
> device_type = "pci";
> dma-coherent;
> num-lanes = <4>;
> + num-ib-windows = <6>;
> + num-ob-windows = <6>;
EP specific properties shouldn't be added in RC dt node. Ideally you should
have a separate dt node for RC and EP.
Thanks
Kishon
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCHv4 1/3] ARMv8: dts: ls1046a: add the property of IB and OB
2017-11-10 6:22 ` Kishon Vijay Abraham I
@ 2017-11-10 21:20 ` Leo Li
[not found] ` <AM4PR0401MB16999BD34AFBB1362BD32EBD8F540-4rsfagO7TJzty7MPzPsMPo3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: Leo Li @ 2017-11-10 21:20 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Xiaowei Bao, robh+dt@kernel.org,
mark.rutland@arm.com, catalin.marinas@arm.com,
will.deacon@arm.com, bhelgaas@google.com, shawnguo@kernel.org,
Madalin-cristian Bucur, Sumit Garg, Y.b. Lu, Andy Tang,
jingoohan1@gmail.com, pbrobinson@gmail.com,
songxiaowei@hisilicon.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
> -----Original Message-----
> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
> Sent: Friday, November 10, 2017 12:22 AM
> To: Xiaowei Bao <xiaowei.bao@nxp.com>; robh+dt@kernel.org;
> mark.rutland@arm.com; catalin.marinas@arm.com; will.deacon@arm.com;
> bhelgaas@google.com; shawnguo@kernel.org; Madalin-cristian Bucur
> <madalin.bucur@nxp.com>; Sumit Garg <sumit.garg@nxp.com>; Y.b. Lu
> <yangbo.lu@nxp.com>; hongtao.jia@nxp.com; Andy Tang
> <andy.tang@nxp.com>; Leo Li <leoyang.li@nxp.com>; jingoohan1@gmail.com;
> pbrobinson@gmail.com; songxiaowei@hisilicon.com;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-pci@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>
> Subject: Re: [PATCHv4 1/3] ARMv8: dts: ls1046a: add the property of IB and OB
>
> Hi Bao,
>
> On Friday 10 November 2017 09:18 AM, Bao Xiaowei wrote:
> > Add the property of inbound and outbound windows number for ep driver.
> >
> > Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
> > Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
> > ---
> > v2:
> > - no change
> > v3:
> > - modify the commit message
> > v4:
> > - no change
> >
> > arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
> > 1 file changed, 6 insertions(+)
>
> $subject should start with something like
> arm64: dts: ls1046a: **
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > index 06b5e12d04d8..f8332669663c 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > @@ -674,6 +674,8 @@
> > device_type = "pci";
> > dma-coherent;
> > num-lanes = <4>;
> > + num-ib-windows = <6>;
> > + num-ob-windows = <6>;
>
> EP specific properties shouldn't be added in RC dt node. Ideally you should have
> a separate dt node for RC and EP.
It is a single PCIe controller which can be configured to either RC mode or EP mode. Wouldn't it conflict with the device tree principles to have two device tree nodes for the same PCIe controller? And obviously the two modes cannot be used at the same time so we cannot have two drivers both probe on the same hardware.
Regards,
Leo
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCHv4 2/3] ARMv8: layerscape: add the pcie ep function support
2017-11-10 3:48 [PATCHv4 0/3] dts: Add the property of IB and OB Bao Xiaowei
2017-11-10 3:48 ` [PATCHv4 1/3] ARMv8: dts: ls1046a: add " Bao Xiaowei
@ 2017-11-10 3:48 ` Bao Xiaowei
2017-11-10 6:31 ` Kishon Vijay Abraham I
2017-11-10 3:48 ` [PATCHv4 3/3] ARMv8: pcie: make the DWC EP driver support for layerscape Bao Xiaowei
2018-11-20 17:30 ` [PATCHv4 0/3] dts: Add the property of IB and OB Lorenzo Pieralisi
3 siblings, 1 reply; 12+ messages in thread
From: Bao Xiaowei @ 2017-11-10 3:48 UTC (permalink / raw)
To: robh+dt, mark.rutland, catalin.marinas, will.deacon, bhelgaas,
shawnguo, madalin.bucur, sumit.garg, yangbo.lu, hongtao.jia,
Yuantian.Tang, leoyang.li, kishon, jingoohan1, pbrobinson,
songxiaowei, devicetree, linux-arm-kernel, linux-kernel,
linux-pci, linuxppc-dev, Zhiqiang.Hou, mingkai.hu, Minghuan.Lian
Cc: Bao Xiaowei
Add the pcie controller ep function support of layerscape base on
pcie ep framework.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
---
v2:
- fix the ioremap function used but no ioumap issue
- optimize the code structure
- add code comments
v3:
- fix the msi outband window request failed issue
v4:
- optimize the code, adjust the format
drivers/pci/dwc/pci-layerscape.c | 120 ++++++++++++++++++++++++++++++++++++---
1 file changed, 113 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 87fa486bee2c..6f3e434599e0 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -34,7 +34,12 @@
/* PEX Internal Configuration Registers */
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
+#define PCIE_DBI2_BASE 0x1000 /* DBI2 base address*/
+#define PCIE_MSI_MSG_DATA_OFF 0x5c /* MSI Data register address*/
+#define PCIE_MSI_OB_SIZE 4096
+#define PCIE_MSI_ADDR_OFFSET (1024 * 1024)
#define PCIE_IATU_NUM 6
+#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000
struct ls_pcie_drvdata {
u32 lut_offset;
@@ -44,12 +49,20 @@ struct ls_pcie_drvdata {
const struct dw_pcie_ops *dw_pcie_ops;
};
+struct ls_pcie_ep {
+ dma_addr_t msi_phys_addr;
+ void __iomem *msi_virt_addr;
+ u64 msi_msg_addr;
+ u16 msi_msg_data;
+};
+
struct ls_pcie {
struct dw_pcie *pci;
void __iomem *lut;
struct regmap *scfg;
const struct ls_pcie_drvdata *drvdata;
int index;
+ struct ls_pcie_ep *pcie_ep;
};
#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
@@ -263,6 +276,99 @@ static const struct of_device_id ls_pcie_of_match[] = {
{ },
};
+static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep)
+{
+ iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr);
+}
+
+static int ls_pcie_raise_irq(struct dw_pcie_ep *ep,
+ enum pci_epc_irq_type type, u8 interrupt_num)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct ls_pcie *pcie = to_ls_pcie(pci);
+ struct ls_pcie_ep *pcie_ep = pcie->pcie_ep;
+ u32 free_win;
+
+ /* get the msi message address and msi message data */
+ pcie_ep->msi_msg_addr = ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_L32) |
+ (((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) << 32);
+ pcie_ep->msi_msg_data = ioread16(pci->dbi_base + PCIE_MSI_MSG_DATA_OFF);
+
+ /* request and config the outband window for msi */
+ free_win = find_first_zero_bit(&ep->ob_window_map,
+ sizeof(ep->ob_window_map));
+ if (free_win >= ep->num_ob_windows) {
+ dev_err(pci->dev, "no free outbound window\n");
+ return -ENOMEM;
+ }
+
+ dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
+ pcie_ep->msi_phys_addr,
+ pcie_ep->msi_msg_addr,
+ PCIE_MSI_OB_SIZE);
+
+ set_bit(free_win, &ep->ob_window_map);
+
+ /* generate the msi interrupt */
+ ls_pcie_raise_msi_irq(pcie_ep);
+
+ /* release the outband window of msi */
+ dw_pcie_disable_atu(pci, free_win, DW_PCIE_REGION_OUTBOUND);
+ clear_bit(free_win, &ep->ob_window_map);
+
+ return 0;
+}
+
+static struct dw_pcie_ep_ops pcie_ep_ops = {
+ .raise_irq = ls_pcie_raise_irq,
+};
+
+static int __init ls_add_pcie_ep(struct ls_pcie *pcie,
+ struct platform_device *pdev)
+{
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ struct dw_pcie_ep *ep;
+ struct ls_pcie_ep *pcie_ep;
+ struct resource *cfg_res;
+ int ret;
+
+ ep = &pci->ep;
+ ep->ops = &pcie_ep_ops;
+
+ pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
+ if (!pcie_ep)
+ return -ENOMEM;
+
+ pcie->pcie_ep = pcie_ep;
+
+ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
+ if (cfg_res) {
+ ep->phys_base = cfg_res->start;
+ ep->addr_size = PCIE_EP_ADDR_SPACE_SIZE;
+ } else {
+ dev_err(dev, "missing *config* space\n");
+ return -ENODEV;
+ }
+
+ pcie_ep->msi_phys_addr = ep->phys_base + PCIE_MSI_ADDR_OFFSET;
+
+ pcie_ep->msi_virt_addr = ioremap(pcie_ep->msi_phys_addr,
+ PCIE_MSI_OB_SIZE);
+ if (!pcie_ep->msi_virt_addr) {
+ dev_err(dev, "failed to map MSI outbound region\n");
+ return -ENOMEM;
+ }
+
+ ret = dw_pcie_ep_init(ep);
+ if (ret) {
+ dev_err(dev, "failed to initialize endpoint\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int __init ls_add_pcie_port(struct ls_pcie *pcie)
{
struct dw_pcie *pci = pcie->pci;
@@ -309,18 +415,18 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
if (IS_ERR(pci->dbi_base))
return PTR_ERR(pci->dbi_base);
- pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
+ pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE;
- if (!ls_pcie_is_bridge(pcie))
- return -ENODEV;
+ pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
platform_set_drvdata(pdev, pcie);
- ret = ls_add_pcie_port(pcie);
- if (ret < 0)
- return ret;
+ if (!ls_pcie_is_bridge(pcie))
+ ret = ls_add_pcie_ep(pcie, pdev);
+ else
+ ret = ls_add_pcie_port(pcie);
- return 0;
+ return ret;
}
static struct platform_driver ls_pcie_driver = {
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCHv4 2/3] ARMv8: layerscape: add the pcie ep function support
2017-11-10 3:48 ` [PATCHv4 2/3] ARMv8: layerscape: add the pcie ep function support Bao Xiaowei
@ 2017-11-10 6:31 ` Kishon Vijay Abraham I
[not found] ` <d02ec499-5de5-11fe-9d95-591513037d49-l0cyMroinI0@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: Kishon Vijay Abraham I @ 2017-11-10 6:31 UTC (permalink / raw)
To: Bao Xiaowei, robh+dt, mark.rutland, catalin.marinas, will.deacon,
bhelgaas, shawnguo, madalin.bucur, sumit.garg, yangbo.lu,
hongtao.jia, Yuantian.Tang, leoyang.li, jingoohan1, pbrobinson,
songxiaowei, devicetree, linux-arm-kernel, linux-kernel,
linux-pci, linuxppc-dev, Zhiqiang.Hou, mingkai.hu, Minghuan.Lian
Hi,
On Friday 10 November 2017 09:18 AM, Bao Xiaowei wrote:
> Add the pcie controller ep function support of layerscape base on
> pcie ep framework.
>
> Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
> ---
> v2:
> - fix the ioremap function used but no ioumap issue
> - optimize the code structure
> - add code comments
> v3:
> - fix the msi outband window request failed issue
> v4:
> - optimize the code, adjust the format
>
> drivers/pci/dwc/pci-layerscape.c | 120 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 113 insertions(+), 7 deletions(-)
$subject should begin with
PCI: layerscape:
>
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> index 87fa486bee2c..6f3e434599e0 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -34,7 +34,12 @@
> /* PEX Internal Configuration Registers */
> #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
>
> +#define PCIE_DBI2_BASE 0x1000 /* DBI2 base address*/
The base address should come from dt.
> +#define PCIE_MSI_MSG_DATA_OFF 0x5c /* MSI Data register address*/
> +#define PCIE_MSI_OB_SIZE 4096
> +#define PCIE_MSI_ADDR_OFFSET (1024 * 1024)
> #define PCIE_IATU_NUM 6
> +#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000
>
> struct ls_pcie_drvdata {
> u32 lut_offset;
> @@ -44,12 +49,20 @@ struct ls_pcie_drvdata {
> const struct dw_pcie_ops *dw_pcie_ops;
> };
>
> +struct ls_pcie_ep {
> + dma_addr_t msi_phys_addr;
> + void __iomem *msi_virt_addr;
> + u64 msi_msg_addr;
> + u16 msi_msg_data;
> +};
> +
> struct ls_pcie {
> struct dw_pcie *pci;
> void __iomem *lut;
> struct regmap *scfg;
> const struct ls_pcie_drvdata *drvdata;
> int index;
> + struct ls_pcie_ep *pcie_ep;
> };
>
> #define to_ls_pcie(x) dev_get_drvdata((x)->dev)
> @@ -263,6 +276,99 @@ static const struct of_device_id ls_pcie_of_match[] = {
> { },
> };
>
> +static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep)
> +{
> + iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr);
> +}
> +
> +static int ls_pcie_raise_irq(struct dw_pcie_ep *ep,
> + enum pci_epc_irq_type type, u8 interrupt_num)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + struct ls_pcie *pcie = to_ls_pcie(pci);
> + struct ls_pcie_ep *pcie_ep = pcie->pcie_ep;
> + u32 free_win;
> +
> + /* get the msi message address and msi message data */
> + pcie_ep->msi_msg_addr = ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_L32) |
> + (((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) << 32);
> + pcie_ep->msi_msg_data = ioread16(pci->dbi_base + PCIE_MSI_MSG_DATA_OFF);
> +
> + /* request and config the outband window for msi */
> + free_win = find_first_zero_bit(&ep->ob_window_map,
> + sizeof(ep->ob_window_map));
> + if (free_win >= ep->num_ob_windows) {
> + dev_err(pci->dev, "no free outbound window\n");
> + return -ENOMEM;
> + }
> +
> + dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
> + pcie_ep->msi_phys_addr,
> + pcie_ep->msi_msg_addr,
> + PCIE_MSI_OB_SIZE);
> +
> + set_bit(free_win, &ep->ob_window_map);
This custom logic is not required. You can use [1] instead
[1] -> https://lkml.org/lkml/2017/11/3/318
> +
> + /* generate the msi interrupt */
> + ls_pcie_raise_msi_irq(pcie_ep);
> +
> + /* release the outband window of msi */
> + dw_pcie_disable_atu(pci, free_win, DW_PCIE_REGION_OUTBOUND);
> + clear_bit(free_win, &ep->ob_window_map);
> +
> + return 0;
> +}
> +
> +static struct dw_pcie_ep_ops pcie_ep_ops = {
> + .raise_irq = ls_pcie_raise_irq,
> +};
> +
> +static int __init ls_add_pcie_ep(struct ls_pcie *pcie,
> + struct platform_device *pdev)
> +{
> + struct dw_pcie *pci = pcie->pci;
> + struct device *dev = pci->dev;
> + struct dw_pcie_ep *ep;
> + struct ls_pcie_ep *pcie_ep;
> + struct resource *cfg_res;
> + int ret;
> +
> + ep = &pci->ep;
> + ep->ops = &pcie_ep_ops;
> +
> + pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
> + if (!pcie_ep)
> + return -ENOMEM;
> +
> + pcie->pcie_ep = pcie_ep;
> +
> + cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> + if (cfg_res) {
> + ep->phys_base = cfg_res->start;
> + ep->addr_size = PCIE_EP_ADDR_SPACE_SIZE;
> + } else {
> + dev_err(dev, "missing *config* space\n");
> + return -ENODEV;
> + }
> +
> + pcie_ep->msi_phys_addr = ep->phys_base + PCIE_MSI_ADDR_OFFSET;
> +
> + pcie_ep->msi_virt_addr = ioremap(pcie_ep->msi_phys_addr,
> + PCIE_MSI_OB_SIZE);
> + if (!pcie_ep->msi_virt_addr) {
> + dev_err(dev, "failed to map MSI outbound region\n");
> + return -ENOMEM;
> + }
> +
> + ret = dw_pcie_ep_init(ep);
> + if (ret) {
> + dev_err(dev, "failed to initialize endpoint\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int __init ls_add_pcie_port(struct ls_pcie *pcie)
> {
> struct dw_pcie *pci = pcie->pci;
> @@ -309,18 +415,18 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
> if (IS_ERR(pci->dbi_base))
> return PTR_ERR(pci->dbi_base);
>
> - pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
> + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE;
>
> - if (!ls_pcie_is_bridge(pcie))
> - return -ENODEV;
> + pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
>
> platform_set_drvdata(pdev, pcie);
>
> - ret = ls_add_pcie_port(pcie);
> - if (ret < 0)
> - return ret;
> + if (!ls_pcie_is_bridge(pcie))
> + ret = ls_add_pcie_ep(pcie, pdev);
HOST or EP mode should be obtained directly from dt.
Thanks
Kishon
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCHv4 3/3] ARMv8: pcie: make the DWC EP driver support for layerscape
2017-11-10 3:48 [PATCHv4 0/3] dts: Add the property of IB and OB Bao Xiaowei
2017-11-10 3:48 ` [PATCHv4 1/3] ARMv8: dts: ls1046a: add " Bao Xiaowei
2017-11-10 3:48 ` [PATCHv4 2/3] ARMv8: layerscape: add the pcie ep function support Bao Xiaowei
@ 2017-11-10 3:48 ` Bao Xiaowei
2018-11-20 17:30 ` [PATCHv4 0/3] dts: Add the property of IB and OB Lorenzo Pieralisi
3 siblings, 0 replies; 12+ messages in thread
From: Bao Xiaowei @ 2017-11-10 3:48 UTC (permalink / raw)
To: robh+dt, mark.rutland, catalin.marinas, will.deacon, bhelgaas,
shawnguo, madalin.bucur, sumit.garg, yangbo.lu, hongtao.jia,
Yuantian.Tang, leoyang.li, kishon, jingoohan1, pbrobinson,
songxiaowei, devicetree, linux-arm-kernel, linux-kernel,
linux-pci, linuxppc-dev, Zhiqiang.Hou, mingkai.hu, Minghuan.Lian
Cc: Bao Xiaowei
Layerscape pcie controllers support RC or EP mode, Add the EP mode
support in Kconfig, the driver will support both RC and EP mode, and
the driver is able to judge the pcie controllers work on RC or EP mode.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
---
v2:
no change
v3:
no change
v4:
no change
drivers/pci/dwc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index 22ec82fcdea2..b5f507795779 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -108,6 +108,7 @@ config PCI_LAYERSCAPE
depends on PCI_MSI_IRQ_DOMAIN
select MFD_SYSCON
select PCIE_DW_HOST
+ select PCIE_DW_EP
help
Say Y here if you want PCIe controller support on Layerscape SoCs.
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCHv4 0/3] dts: Add the property of IB and OB
2017-11-10 3:48 [PATCHv4 0/3] dts: Add the property of IB and OB Bao Xiaowei
` (2 preceding siblings ...)
2017-11-10 3:48 ` [PATCHv4 3/3] ARMv8: pcie: make the DWC EP driver support for layerscape Bao Xiaowei
@ 2018-11-20 17:30 ` Lorenzo Pieralisi
2018-11-22 2:33 ` Xiaowei Bao
3 siblings, 1 reply; 12+ messages in thread
From: Lorenzo Pieralisi @ 2018-11-20 17:30 UTC (permalink / raw)
To: Bao Xiaowei
Cc: robh+dt, mark.rutland, catalin.marinas, will.deacon, bhelgaas,
shawnguo, madalin.bucur, sumit.garg, yangbo.lu, hongtao.jia,
Yuantian.Tang, leoyang.li, kishon, jingoohan1, pbrobinson,
songxiaowei, devicetree, linux-arm-kernel, linux-kernel,
linux-pci, linuxppc-dev, Zhiqiang.Hou, mingkai.hu, Minghuan.Lian
On Fri, Nov 10, 2017 at 11:48:44AM +0800, Bao Xiaowei wrote:
> Depend on http://patchwork.ozlabs.org/patch/815382/
>
> Bao Xiaowei (3):
> ARMv8: dts: ls1046a: add the property of IB and OB
> ARMv8: layerscape: add the pcie ep function support
> ARMv8: pcie: make the DWC EP driver support for layerscape
>
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++
> drivers/pci/dwc/Kconfig | 1 +
> drivers/pci/dwc/pci-layerscape.c | 121 +++++++++++++++++++++++--
> 3 files changed, 121 insertions(+), 7 deletions(-)
Can I drop this series from the linux-pci patch queue ? I reckon
it is superseded by:
https://patchwork.ozlabs.org/patch/992928/
but I wanted to make sure that's the case, I really can't follow
the version numbering so I am asking.
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCHv4 0/3] dts: Add the property of IB and OB
2018-11-20 17:30 ` [PATCHv4 0/3] dts: Add the property of IB and OB Lorenzo Pieralisi
@ 2018-11-22 2:33 ` Xiaowei Bao
0 siblings, 0 replies; 12+ messages in thread
From: Xiaowei Bao @ 2018-11-22 2:33 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com,
will.deacon@arm.com, bhelgaas@google.com, shawnguo@kernel.org,
Madalin-cristian Bucur, sumit.garg@nxp.com, Y.B. LU,
hongtao.jia@nxp.com, Andy Tang, Leo Li, kishon@ti.com,
jingoohan1@gmail.com, pbrobinson@gmail.com,
songxiaowei@hisilicon.com, devicetree@vger.kernel.org,
linux-arm-kernel
Hi Lorenzo,
Yes, these series patches can drop, thanks a lot.
Best regards
Xiaowei
-----Original Message-----
From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Sent: 2018年11月21日 1:31
To: Xiaowei Bao <xiaowei.bao@nxp.com>
Cc: robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com; will.deacon@arm.com; bhelgaas@google.com; shawnguo@kernel.org; Madalin-cristian Bucur <madalin.bucur@nxp.com>; sumit.garg@nxp.com; Y.B. LU <yangbo.lu@nxp.com>; hongtao.jia@nxp.com; Andy Tang <andy.tang@nxp.com>; Leo Li <leoyang.li@nxp.com>; kishon@ti.com; jingoohan1@gmail.com; pbrobinson@gmail.com; songxiaowei@hisilicon.com; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-pci@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>
Subject: Re: [PATCHv4 0/3] dts: Add the property of IB and OB
On Fri, Nov 10, 2017 at 11:48:44AM +0800, Bao Xiaowei wrote:
> Depend on
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatc
> hwork.ozlabs.org%2Fpatch%2F815382%2F&data=02%7C01%7Cxiaowei.bao%40
> nxp.com%7C675188594567418ccf6a08d64f0de9f5%7C686ea1d3bc2b4c6fa92cd99c5
> c301635%7C0%7C0%7C636783318517192971&sdata=HilLT%2B5T%2B%2Bubpxra8
> l54ZViEFN7SBCf4vDB8zDMWUd4%3D&reserved=0
>
> Bao Xiaowei (3):
> ARMv8: dts: ls1046a: add the property of IB and OB
> ARMv8: layerscape: add the pcie ep function support
> ARMv8: pcie: make the DWC EP driver support for layerscape
>
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++
> drivers/pci/dwc/Kconfig | 1 +
> drivers/pci/dwc/pci-layerscape.c | 121 +++++++++++++++++++++++--
> 3 files changed, 121 insertions(+), 7 deletions(-)
Can I drop this series from the linux-pci patch queue ? I reckon it is superseded by:
https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F992928%2F&data=02%7C01%7Cxiaowei.bao%40nxp.com%7C675188594567418ccf6a08d64f0de9f5%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636783318517192971&sdata=i3U%2F7uT%2Fno%2FSGVc6VD1gg7Ybn0zV%2F%2B8A9698QHfuoTo%3D&reserved=0
but I wanted to make sure that's the case, I really can't follow the version numbering so I am asking.
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 12+ messages in thread