From: Bao Xiaowei <xiaowei.bao@nxp.com>
To: robh+dt@kernel.org, mark.rutland@arm.com,
catalin.marinas@arm.com, will.deacon@arm.com,
bhelgaas@google.com, shawnguo@kernel.org, madalin.bucur@nxp.com,
sumit.garg@nxp.com, yangbo.lu@nxp.com, hongtao.jia@nxp.com,
Yuantian.Tang@nxp.com, leoyang.li@nxp.com, kishon@ti.com,
jingoohan1@gmail.com, pbrobinson@gmail.com,
songxiaowei@hisilicon.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, Zhiqiang.Hou@nxp.com,
mingkai.hu@nxp.com, Minghuan.Lian@nxp.com
Cc: Bao Xiaowei <xiaowei.bao@nxp.com>
Subject: [PATCHv4 1/3] ARMv8: dts: ls1046a: add the property of IB and OB
Date: Fri, 10 Nov 2017 11:48:45 +0800 [thread overview]
Message-ID: <20171110034847.17891-2-xiaowei.bao@nxp.com> (raw)
In-Reply-To: <20171110034847.17891-1-xiaowei.bao@nxp.com>
Add the property of inbound and outbound windows number for ep
driver.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
---
v2:
- no change
v3:
- modify the commit message
v4:
- no change
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 06b5e12d04d8..f8332669663c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -674,6 +674,8 @@
device_type = "pci";
dma-coherent;
num-lanes = <4>;
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -699,6 +701,8 @@
device_type = "pci";
dma-coherent;
num-lanes = <2>;
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -724,6 +728,8 @@
device_type = "pci";
dma-coherent;
num-lanes = <2>;
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
--
2.14.1
next prev parent reply other threads:[~2017-11-10 3:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-10 3:48 [PATCHv4 0/3] dts: Add the property of IB and OB Bao Xiaowei
2017-11-10 3:48 ` Bao Xiaowei [this message]
2017-11-10 6:22 ` [PATCHv4 1/3] ARMv8: dts: ls1046a: add " Kishon Vijay Abraham I
2017-11-10 21:20 ` Leo Li
[not found] ` <AM4PR0401MB16999BD34AFBB1362BD32EBD8F540-4rsfagO7TJzty7MPzPsMPo3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2017-11-13 2:35 ` M.h. Lian
2017-11-16 16:49 ` Lorenzo Pieralisi
2017-11-10 3:48 ` [PATCHv4 2/3] ARMv8: layerscape: add the pcie ep function support Bao Xiaowei
2017-11-10 6:31 ` Kishon Vijay Abraham I
[not found] ` <d02ec499-5de5-11fe-9d95-591513037d49-l0cyMroinI0@public.gmane.org>
2017-11-13 4:02 ` Xiaowei Bao
2017-11-10 3:48 ` [PATCHv4 3/3] ARMv8: pcie: make the DWC EP driver support for layerscape Bao Xiaowei
2018-11-20 17:30 ` [PATCHv4 0/3] dts: Add the property of IB and OB Lorenzo Pieralisi
2018-11-22 2:33 ` Xiaowei Bao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171110034847.17891-2-xiaowei.bao@nxp.com \
--to=xiaowei.bao@nxp.com \
--cc=Minghuan.Lian@nxp.com \
--cc=Yuantian.Tang@nxp.com \
--cc=Zhiqiang.Hou@nxp.com \
--cc=bhelgaas@google.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=hongtao.jia@nxp.com \
--cc=jingoohan1@gmail.com \
--cc=kishon@ti.com \
--cc=leoyang.li@nxp.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=madalin.bucur@nxp.com \
--cc=mark.rutland@arm.com \
--cc=mingkai.hu@nxp.com \
--cc=pbrobinson@gmail.com \
--cc=robh+dt@kernel.org \
--cc=shawnguo@kernel.org \
--cc=songxiaowei@hisilicon.com \
--cc=sumit.garg@nxp.com \
--cc=will.deacon@arm.com \
--cc=yangbo.lu@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).