From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Simon Horman <horms@verge.net.au>,
Rob Herring <robh+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org
Cc: Magnus Damm <magnus.damm@gmail.com>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org,
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: [PATCH 2/3] arm64: dts: renesas: eagle: add SCIF0 pins
Date: Fri, 10 Nov 2017 23:02:20 +0300 [thread overview]
Message-ID: <20171110200710.769271617@cogentembedded.com> (raw)
[-- Attachment #1: arm64-dts-renesas-eagle-add-SCIF0-pins.patch --]
[-- Type: text/plain, Size: 800 bytes --]
Add the (previously omitted) SCIF0 pin data to the Eagle board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -52,11 +52,21 @@
clock-frequency = <32768>;
};
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+};
+
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
next reply other threads:[~2017-11-10 20:02 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-10 20:02 Sergei Shtylyov [this message]
2017-11-14 8:34 ` [PATCH 2/3] arm64: dts: renesas: eagle: add SCIF0 pins Geert Uytterhoeven
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