From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yixun Lan Subject: [PATCH v5 1/2] ARM64: dts: meson: drop "sana" clock from SAR ADC Date: Thu, 16 Nov 2017 17:01:14 +0800 Message-ID: <20171116090115.29915-2-yixun.lan@amlogic.com> References: <20171116090115.29915-1-yixun.lan@amlogic.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20171116090115.29915-1-yixun.lan@amlogic.com> Sender: linux-kernel-owner@vger.kernel.org To: Kevin Hilman , devicetree@vger.kernel.org Cc: Neil Armstrong , Jerome Brunet , Rob Herring , Mark Rutland , Martin Blumenstingl , Carlo Caione , Yixun Lan , Xingyu Chen , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org From: Xingyu Chen The SAR ADC modules doesn't require The "sana" clock. Acked-by: Martin Blumenstingl Singed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 3 +-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index af834cdbba79..b77f2593cdc3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -686,10 +686,9 @@ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; clocks = <&xtal>, <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>, <&clkc CLKID_SAR_ADC_CLK>, <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; }; &sd_emmc_a { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index d8dd3298b15c..07805a3b4db0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -628,10 +628,9 @@ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; clocks = <&xtal>, <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>, <&clkc CLKID_SAR_ADC_CLK>, <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; }; &sd_emmc_a { -- 2.14.1