From mboxrd@z Thu Jan 1 00:00:00 1970 From: Quentin Schulz Subject: [PATCH v5 6/9] pinctrl: axp209: add programmable gpio_status_offset Date: Tue, 5 Dec 2017 15:46:44 +0100 Message-ID: <20171205144647.17594-7-quentin.schulz@free-electrons.com> References: <20171205144647.17594-1-quentin.schulz@free-electrons.com> Reply-To: quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20171205144647.17594-1-quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Quentin Schulz List-Id: devicetree@vger.kernel.org To prepare for patches that will add support for a new PMIC that has a different GPIO input status register, add a gpio_status_offset within axp20x_pctl structure and use it. Signed-off-by: Quentin Schulz Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- drivers/pinctrl/pinctrl-axp209.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index 17eeb0410a5b..db8e319b6e11 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -48,6 +48,7 @@ struct axp20x_pctrl_desc { u8 ldo_mask; /* Stores the pins supporting ADC function. Bit offset is pin number. */ u8 adc_mask; + u8 gpio_status_offset; }; struct axp20x_pinctrl_function { @@ -77,6 +78,7 @@ static const struct axp20x_pctrl_desc axp20x_data = { .npins = ARRAY_SIZE(axp209_pins), .ldo_mask = BIT(0) | BIT(1), .adc_mask = BIT(0) | BIT(1), + .gpio_status_offset = 4, }; static int axp20x_gpio_get_reg(unsigned int offset) @@ -108,7 +110,7 @@ static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset) if (ret) return ret; - return !!(val & BIT(offset + 4)); + return !!(val & BIT(offset + pctl->desc->gpio_status_offset)); } static int axp20x_gpio_get_direction(struct gpio_chip *chip, -- 2.14.1