From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0 Date: Wed, 13 Dec 2017 16:40:35 +0100 Message-ID: <20171213154035.qc655iahjoeflftq@flea.lan> References: <1513151074-6888-1-git-send-email-stefan@olimex.com> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="xzxickwhi7u6xbxo" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <1513151074-6888-1-git-send-email-stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Stefan Mavrodiev Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Rob Herring , Mark Rutland , Russell King , Chen-Yu Tsai , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM PORT" , open list List-Id: devicetree@vger.kernel.org --xzxickwhi7u6xbxo Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline Hi, On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote: > Allwinner A10/A13/A20 SoCs have pinmux for spi0 > on port C. The patch adds these pins in the respective > dts includes. > > Signed-off-by: Stefan Mavrodiev Do you have any boards that are using these? We won't merge that patch if there's no users for it. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --xzxickwhi7u6xbxo--