From: Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Cc: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
hongkun.cao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
yu.yu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
xinping.qian-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH v2 2/2] PCI: mediatek: Fixup class type for MT7622
Date: Thu, 21 Dec 2017 21:15:47 -0600 [thread overview]
Message-ID: <20171222031546.GF30595@bhelgaas-glaptop.roam.corp.google.com> (raw)
In-Reply-To: <1513904194.25872.23.camel@mhfsdcap03>
On Fri, Dec 22, 2017 at 08:56:34AM +0800, Honghui Zhang wrote:
> There's an internal control register that control the Vendor ID and
> device ID values, our designer leave the default value un-touched. I
> will set these values in that way for the next version of fix.
Then there's no problem. The mtk_pcie driver is a platform driver
that claims the host controller based on an of_device_id from a device
tree.
Apparently the bridge is also materialized in PCI config space, which
is typical for x86 host bridges, and makes the bridge appear in
"lspci". But drivers generally don't claim bridges that way.
You can just program the Vendor and Device IDs by writing the internal
control registers somewhere in the mtk_pci_probe() path.
Then you can set the class code the same way, using an internal
control register (if that's possible), or using a quirk with the
correct Mediatek Vendor ID (if there is no internal writable
register).
Bjorn
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next prev parent reply other threads:[~2017-12-22 3:15 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-21 2:11 [PATCH v2 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code honghui.zhang
[not found] ` <1513822277-18329-1-git-send-email-honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-12-21 2:11 ` [PATCH v2 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
2017-12-21 2:11 ` [PATCH v2 2/2] PCI: mediatek: Fixup class type for MT7622 honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
2017-12-21 6:41 ` Yong Wu
2017-12-21 7:01 ` Honghui Zhang
2017-12-22 0:27 ` Bjorn Helgaas
2017-12-22 0:56 ` Honghui Zhang
2017-12-22 3:15 ` Bjorn Helgaas [this message]
-- strict thread matches above, loose matches on Subject: below --
2017-12-21 2:08 [PATCH v2 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
[not found] ` <1513822130-18213-1-git-send-email-honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-12-21 2:08 ` [PATCH v2 2/2] PCI: mediatek: Fixup class type for MT7622 honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
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