[PATCHv1 0/6] GEHC Bx50 Switch Support

[PATCHv1 0/6] GEHC Bx50 Switch Support

[Sebastian Reichel]

Hi,

This adds support for the internal switch found in GE Healthcare
B450v3, B650v3 and B850v3. All devices use a GPIO bitbanged MDIO
bus to communicate with the switch and a PCIe based network card
for exchanging network data. The cpu network data link requires,
that the switch's internal phy interface is enabled, so support
for that is added by the first patch in this series.

The patch series is based on v4.15-rc6.

-- Sebastian

Sebastian Reichel (6):
  net: dsa: Support internal phy on 'cpu' port
  net: dsa: mv88e6xxx: add 88E6240 DT compatible
  ARM: dts: imx6q-bx50v3: Add internal switch
  ARM: dts: imx6q-b850v3: Add switch port configuration
  ARM: dts: imx6q-b650v3: Add switch port configuration
  ARM: dts: imx6q-b450v3: Add switch port configuration

 .../devicetree/bindings/net/dsa/marvell.txt        |  6 +-
 arch/arm/boot/dts/imx6q-b450v3.dts                 | 47 +++++++++++++++
 arch/arm/boot/dts/imx6q-b650v3.dts                 | 47 +++++++++++++++
 arch/arm/boot/dts/imx6q-b850v3.dts                 | 70 ++++++++++++++++++++++
 arch/arm/boot/dts/imx6q-bx50v3.dtsi                | 37 ++++++++++++
 drivers/net/dsa/mv88e6xxx/chip.c                   |  4 ++
 net/dsa/port.c                                     | 26 ++++++--
 7 files changed, 231 insertions(+), 6 deletions(-)

-- 
2.15.1

[PATCHv1 1/6] net: dsa: Support internal phy on 'cpu' port

[Sebastian Reichel]

This adds support for enabling the internal phy for a 'cpu' port.
It has been tested on GE B850v3 and B650v3, which have a built-in
MV88E6240 switch connected to a PCIe based network card. Without
this patch the link does not come up and no traffic can be routed
through the switch.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 net/dsa/port.c | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/net/dsa/port.c b/net/dsa/port.c
index bb4be2679904..f99c1d34416c 100644
--- a/net/dsa/port.c
+++ b/net/dsa/port.c
@@ -282,6 +282,10 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
 	int mode;
 	int err;
 
+	mode = of_get_phy_mode(dn);
+	if (mode < 0)
+		mode = PHY_INTERFACE_MODE_NA;
+
 	if (of_phy_is_fixed_link(dn)) {
 		err = of_phy_register_fixed_link(dn);
 		if (err) {
@@ -292,10 +296,6 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
 		}
 
 		phydev = of_phy_find_device(dn);
-
-		mode = of_get_phy_mode(dn);
-		if (mode < 0)
-			mode = PHY_INTERFACE_MODE_NA;
 		phydev->interface = mode;
 
 		genphy_config_init(phydev);
@@ -305,6 +305,24 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
 			ds->ops->adjust_link(ds, port, phydev);
 
 		put_device(&phydev->mdio.dev);
+	} else if (mode == PHY_INTERFACE_MODE_INTERNAL ||
+		   mode == PHY_INTERFACE_MODE_NA) {
+		phydev = mdiobus_get_phy(ds->slave_mii_bus, port);
+		if (phydev) {
+			genphy_config_init(phydev);
+			genphy_resume(phydev);
+			genphy_read_status(phydev);
+
+			if (ds->ops->adjust_link)
+				ds->ops->adjust_link(ds, port, phydev);
+
+			dev_dbg(ds->dev, "enabled cpu port's phy: %s",
+				phydev_name(phydev));
+		} else {
+			dev_warn(ds->dev, "cpu port has no internal phy and no fixed linked has been configured!");
+		}
+	} else {
+		dev_err(ds->dev, "unsupported phy mode!");
 	}
 
 	return 0;
-- 
2.15.1

Re: [PATCHv1 1/6] net: dsa: Support internal phy on 'cpu' port

[Andrew Lunn]

On Wed, Jan 03, 2018 at 01:26:04PM +0100, Sebastian Reichel wrote:
> This adds support for enabling the internal phy for a 'cpu' port.
> It has been tested on GE B850v3 and B650v3, which have a built-in
> MV88E6240 switch connected to a PCIe based network card. Without
> this patch the link does not come up and no traffic can be routed
> through the switch.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>
> ---
>  net/dsa/port.c | 26 ++++++++++++++++++++++----
>  1 file changed, 22 insertions(+), 4 deletions(-)
> 
> diff --git a/net/dsa/port.c b/net/dsa/port.c
> index bb4be2679904..f99c1d34416c 100644
> --- a/net/dsa/port.c
> +++ b/net/dsa/port.c
> @@ -282,6 +282,10 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
>  	int mode;
>  	int err;
>  
> +	mode = of_get_phy_mode(dn);
> +	if (mode < 0)
> +		mode = PHY_INTERFACE_MODE_NA;
> +
>  	if (of_phy_is_fixed_link(dn)) {
>  		err = of_phy_register_fixed_link(dn);
>  		if (err) {
> @@ -292,10 +296,6 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
>  		}
>  
>  		phydev = of_phy_find_device(dn);
> -
> -		mode = of_get_phy_mode(dn);
> -		if (mode < 0)
> -			mode = PHY_INTERFACE_MODE_NA;
>  		phydev->interface = mode;
>  
>  		genphy_config_init(phydev);
> @@ -305,6 +305,24 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
>  			ds->ops->adjust_link(ds, port, phydev);
>  
>  		put_device(&phydev->mdio.dev);
> +	} else if (mode == PHY_INTERFACE_MODE_INTERNAL ||
> +		   mode == PHY_INTERFACE_MODE_NA) {

Hi Sebastian

I understand what you are trying to do, i've got boards which also
have back-to-back PHYs for the CPU port. These boards however have the
strapping correct, so nothing needs doing in software.

But the way you are doing it is wrong. PHY_INTERFACE_MODE_NA means
something else has already setup the interface mode, leave it alone.
PHY_INTERFACE_MODE_INTERNAL means there is some other sort of bus
between the MAC and the PHY than the normal MII.

What you want to say is that there is a PHY on this port, and that you
want to configure it to a given fixed configuration, probably 1000
Full, with auto-neg turned off. This is something completely different
to a fixed phy, which is used when there is no PHY at all.

What state is the PHY in, if you don't have this patch? Is it powered
down?

	Andrew
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Re: [PATCHv1 1/6] net: dsa: Support internal phy on 'cpu' port

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 3868 bytes --]

Hi Andrew,

On Wed, Jan 03, 2018 at 02:21:28PM +0100, Andrew Lunn wrote:
> On Wed, Jan 03, 2018 at 01:26:04PM +0100, Sebastian Reichel wrote:
> > This adds support for enabling the internal phy for a 'cpu' port.
> > It has been tested on GE B850v3 and B650v3, which have a built-in
> > MV88E6240 switch connected to a PCIe based network card. Without
> > this patch the link does not come up and no traffic can be routed
> > through the switch.
> > 
> > Signed-off-by: Sebastian Reichel <sebastian.reichel-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>
> > ---
> >  net/dsa/port.c | 26 ++++++++++++++++++++++----
> >  1 file changed, 22 insertions(+), 4 deletions(-)
> > 
> > diff --git a/net/dsa/port.c b/net/dsa/port.c
> > index bb4be2679904..f99c1d34416c 100644
> > --- a/net/dsa/port.c
> > +++ b/net/dsa/port.c
> > @@ -282,6 +282,10 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
> >  	int mode;
> >  	int err;
> >  
> > +	mode = of_get_phy_mode(dn);
> > +	if (mode < 0)
> > +		mode = PHY_INTERFACE_MODE_NA;
> > +
> >  	if (of_phy_is_fixed_link(dn)) {
> >  		err = of_phy_register_fixed_link(dn);
> >  		if (err) {
> > @@ -292,10 +296,6 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
> >  		}
> >  
> >  		phydev = of_phy_find_device(dn);
> > -
> > -		mode = of_get_phy_mode(dn);
> > -		if (mode < 0)
> > -			mode = PHY_INTERFACE_MODE_NA;
> >  		phydev->interface = mode;
> >  
> >  		genphy_config_init(phydev);
> > @@ -305,6 +305,24 @@ int dsa_port_fixed_link_register_of(struct dsa_port *dp)
> >  			ds->ops->adjust_link(ds, port, phydev);
> >  
> >  		put_device(&phydev->mdio.dev);
> > +	} else if (mode == PHY_INTERFACE_MODE_INTERNAL ||
> > +		   mode == PHY_INTERFACE_MODE_NA) {
> 
> Hi Sebastian
> 
> I understand what you are trying to do, i've got boards which also
> have back-to-back PHYs for the CPU port. These boards however have the
> strapping correct, so nothing needs doing in software.

What I have is a PCIe intel network card with phy, that is wired to a
mv88e6240 switch. The network card is exposed as normal network device,
so phy is enabled when the interface is brought up. The 'cpu' port
for mv88e6240 has an integrated phy, that needs to be enabled.

Your boards must be different, since mv88e6xxx is being reset during
probe(). So even if the 'cpu' phy was enabled before driver probe(),
it would be disabled afterwards.

> But the way you are doing it is wrong. PHY_INTERFACE_MODE_NA means
> something else has already setup the interface mode, leave it alone.

Ok, I assumed, that PHY_INTERFACE_MODE_NA means "no explicit
configuration found, use implicit configuration". E.g. for
mv88e6xxx the downstream ports are not configured in DT, but
their PHY is enabled.

> PHY_INTERFACE_MODE_INTERNAL means there is some other sort of bus
> between the MAC and the PHY than the normal MII.
> 
> What you want to say is that there is a PHY on this port, and that you
> want to configure it to a given fixed configuration, probably 1000
> Full, with auto-neg turned off. This is something completely different
> to a fixed phy, which is used when there is no PHY at all.

That's why I put the new code into

if (of_phy_is_fixed_link(...)) {
    <<< old code >>>
} else {
    <<< new code >>>
}

I agree, that the function name dsa_port_fixed_link_register_of() is
a bit confusing with the added code. I actually added this to
dsa_cpu_dsa_setup() and with the rebase to current master it ended
up there.

> What state is the PHY in, if you don't have this patch? Is it powered
> down?

The phy is part of mv88e6240, which is being reset during probe.
So the phy is powered down and DSA is not functional except for
phy information of downstream ports. The PCIe network interface
does not detect a carrier.

-- Sebastian

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[PATCHv1 2/6] net: dsa: mv88e6xxx: add 88E6240 DT compatible

[Sebastian Reichel]

Add compatible for Marvell 88E6240 switch.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 Documentation/devicetree/bindings/net/dsa/marvell.txt | 6 ++++--
 drivers/net/dsa/mv88e6xxx/chip.c                      | 4 ++++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt
index 1d4d0f49c9d0..cf437b526f7f 100644
--- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
+++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
@@ -14,8 +14,10 @@ The properties described here are those specific to Marvell devices.
 Additional required and optional properties can be found in dsa.txt.
 
 Required properties:
-- compatible		: Should be one of "marvell,mv88e6085" or
-			  "marvell,mv88e6190"
+- compatible		: Should be one of the following
+ * "marvell,mv88e6085"
+ * "marvell,mv88e6190"
+ * "marvell,mv88e6240"
 - reg			: Address on the MII bus for the switch.
 
 Optional properties:
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 66d33e97cbc5..78ff06239b58 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -4012,6 +4012,10 @@ static const struct of_device_id mv88e6xxx_of_match[] = {
 		.compatible = "marvell,mv88e6190",
 		.data = &mv88e6xxx_table[MV88E6190],
 	},
+	{
+		.compatible = "marvell,mv88e6240",
+		.data = &mv88e6xxx_table[MV88E6240],
+	},
 	{ /* sentinel */ },
 };
 
-- 
2.15.1

Re: [PATCHv1 2/6] net: dsa: mv88e6xxx: add 88E6240 DT compatible

[Andrew Lunn]

On Wed, Jan 03, 2018 at 01:26:05PM +0100, Sebastian Reichel wrote:
> Add compatible for Marvell 88E6240 switch.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/net/dsa/marvell.txt | 6 ++++--
>  drivers/net/dsa/mv88e6xxx/chip.c                      | 4 ++++
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt
> index 1d4d0f49c9d0..cf437b526f7f 100644
> --- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
> +++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
> @@ -14,8 +14,10 @@ The properties described here are those specific to Marvell devices.
>  Additional required and optional properties can be found in dsa.txt.
>  
>  Required properties:
> -- compatible		: Should be one of "marvell,mv88e6085" or
> -			  "marvell,mv88e6190"
> +- compatible		: Should be one of the following
> + * "marvell,mv88e6085"
> + * "marvell,mv88e6190"
> + * "marvell,mv88e6240"

Hi Sebastian

This is not required. The 6240 is compatible with the 6085, so please
use "marvell,mv88e6085". We don't add compatible strings per
device. All the compatible string is used for is to find the ID
register in the device. Nothing more.

	Andrew
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[PATCHv1 3/6] ARM: dts: imx6q-bx50v3: Add internal switch

[Sebastian Reichel]

B850v3, B650v3 and B450v3 all have a GPIO bit banged MDIO bus to
communicate with a Marvell switch. On all devices the switch is
connected to a PCI based network card, which needs to be referenced
by DT, so this also adds the common PCI root node.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 arch/arm/boot/dts/imx6q-bx50v3.dtsi | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index b915837bbb5f..689981e90e68 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -92,6 +92,31 @@
 		mux-int-port = <1>;
 		mux-ext-port = <4>;
 	};
+
+	aliases {
+		mdio-gpio0 = &mdio0;
+	};
+
+	mdio0: mdio-gpio {
+		compatible = "virtual,mdio-gpio";
+		gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
+			<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch@0 {
+				compatible = "marvell,mv88e6240";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>;
+
+				switch_ports: ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+		};
+	};
 };
 
 &ecspi5 {
@@ -326,3 +351,15 @@
 		tcxo-clock-frequency = <26000000>;
 	};
 };
+
+&pcie {
+	/* Synopsys, Inc. Device */
+	pci_root: root@0,0 {
+		compatible = "pci16c3,abcd";
+		reg = <0x00000000 0 0 0 0>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+	};
+};
-- 
2.15.1

Re: [PATCHv1 3/6] ARM: dts: imx6q-bx50v3: Add internal switch

[Sergei Shtylyov]

Hello!

On 01/03/2018 03:26 PM, Sebastian Reichel wrote:

> B850v3, B650v3 and B450v3 all have a GPIO bit banged MDIO bus to
> communicate with a Marvell switch. On all devices the switch is
> connected to a PCI based network card, which needs to be referenced
> by DT, so this also adds the common PCI root node.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>
> ---
>   arch/arm/boot/dts/imx6q-bx50v3.dtsi | 37 +++++++++++++++++++++++++++++++++++++
>   1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
> index b915837bbb5f..689981e90e68 100644
> --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
> +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
> @@ -92,6 +92,31 @@
>   		mux-int-port = <1>;
>   		mux-ext-port = <4>;
>   	};
> +
> +	aliases {
> +		mdio-gpio0 = &mdio0;
> +	};
> +
> +	mdio0: mdio-gpio {
> +		compatible = "virtual,mdio-gpio";
> +		gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
> +			<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
> +
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		switch@0 {
> +				compatible = "marvell,mv88e6240";

    Why suddenly 2 extra tabs instead of 1?

> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0>;
> +
> +				switch_ports: ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +		};
> +	};
>   };
>   
>   &ecspi5 {
[...]

MBR, Sergei
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Re: [PATCHv1 3/6] ARM: dts: imx6q-bx50v3: Add internal switch

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 1702 bytes --]

Hi,

On Wed, Jan 03, 2018 at 05:48:42PM +0300, Sergei Shtylyov wrote:
> Hello!
> 
> On 01/03/2018 03:26 PM, Sebastian Reichel wrote:
> 
> > B850v3, B650v3 and B450v3 all have a GPIO bit banged MDIO bus to
> > communicate with a Marvell switch. On all devices the switch is
> > connected to a PCI based network card, which needs to be referenced
> > by DT, so this also adds the common PCI root node.
> > 
> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
> > ---
> >   arch/arm/boot/dts/imx6q-bx50v3.dtsi | 37 +++++++++++++++++++++++++++++++++++++
> >   1 file changed, 37 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
> > index b915837bbb5f..689981e90e68 100644
> > --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
> > +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
> > @@ -92,6 +92,31 @@
> >   		mux-int-port = <1>;
> >   		mux-ext-port = <4>;
> >   	};
> > +
> > +	aliases {
> > +		mdio-gpio0 = &mdio0;
> > +	};
> > +
> > +	mdio0: mdio-gpio {
> > +		compatible = "virtual,mdio-gpio";
> > +		gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
> > +			<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
> > +
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		switch@0 {
> > +				compatible = "marvell,mv88e6240";
> 
>    Why suddenly 2 extra tabs instead of 1?

will be fixed in PATCHv2.

> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				reg = <0>;
> > +
> > +				switch_ports: ports {
> > +					#address-cells = <1>;
> > +					#size-cells = <0>;
> > +				};
> > +		};
> > +	};
> >   };
> >   &ecspi5 {
> [...]
> 
> MBR, Sergei

-- Sebastian

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[PATCHv1 4/6] ARM: dts: imx6q-b850v3: Add switch port configuration

[Sebastian Reichel]

This adds support for the Marvell switch and names the network
ports according to the labels, that can be found next to the
connectors ("ID", "IX", "ePort 1", "ePort 2"). The switch is
connected to the host system using a PCI based network card.

The PCI bus configuration has been written using the following
information:

root@b850v3# lspci -tv
-[0000:00]---00.0-[01]----00.0-[02-05]--+-01.0-[03]----00.0  Intel Corporation I210 Gigabit Network Connection
                                        +-02.0-[04]----00.0  Intel Corporation I210 Gigabit Network Connection
                                        \-03.0-[05]--
root@b850v3# lspci -nn
00:00.0 PCI bridge [0604]: Synopsys, Inc. Device [16c3:abcd] (rev 01)
01:00.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
02:01.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
02:02.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
02:03.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
03:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)
04:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 arch/arm/boot/dts/imx6q-b850v3.dts | 70 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
index 46bdc6722715..a55ccdfb341c 100644
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -212,3 +212,73 @@
 		};
 	};
 };
+
+&pci_root {
+	/* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
+	bridge@1,0 {
+		compatible = "pci10b5,8605";
+		reg = <0x00010000 0 0 0 0>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+
+		bridge@2,1 {
+			compatible = "pci10b5,8605";
+			reg = <0x00020800 0 0 0 0>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+
+			/* Intel Corporation I210 Gigabit Network Connection */
+			ethernet@3,0 {
+				compatible = "pci8086,1533";
+				reg = <0x00030000 0 0 0 0>;
+			};
+		};
+
+		bridge@2,2 {
+			compatible = "pci10b5,8605";
+			reg = <0x00021000 0 0 0 0>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+
+			/* Intel Corporation I210 Gigabit Network Connection */
+			switch_nic: ethernet@4,0 {
+				compatible = "pci8086,1533";
+				reg = <0x00040000 0 0 0 0>;
+			};
+		};
+	};
+};
+
+&switch_ports {
+	port@0 {
+		reg = <0>;
+		label = "eneport1";
+	};
+
+	port@1 {
+		reg = <1>;
+		label = "eneport2";
+	};
+
+	port@2 {
+		reg = <2>;
+		label = "enix";
+	};
+
+	port@3 {
+		reg = <3>;
+		label = "enid";
+	};
+
+	port@4 {
+		reg = <4>;
+		label = "cpu";
+		ethernet = <&switch_nic>;
+	};
+};
-- 
2.15.1

[PATCHv1 5/6] ARM: dts: imx6q-b650v3: Add switch port configuration

[Sebastian Reichel]

This adds support for the Marvell switch and names the network
ports according to the labels, that can be found next to the
connectors. The switch is connected to the host system using a
PCI based network card.

The PCI bus configuration has been written using the following
information:

root@b650v3# lspci -tv
-[0000:00]---00.0-[01]----00.0  Intel Corporation I210 Gigabit Network Connection
root@b650v3# lspci -nn
00:00.0 PCI bridge [0604]: Synopsys, Inc. Device [16c3:abcd] (rev 01)
01:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 arch/arm/boot/dts/imx6q-b650v3.dts | 47 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
index 7f9f176901d4..928f6cd8d5ae 100644
--- a/arch/arm/boot/dts/imx6q-b650v3.dts
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -111,3 +111,50 @@
 	fsl,tx-cal-45-dp-ohms = <55>;
 	fsl,tx-d-cal = <100>;
 };
+
+&pci_root {
+	/* Intel Corporation I210 Gigabit Network Connection */
+	switch_nic: ethernet@3,0 {
+		compatible = "pci8086,1533";
+		reg = <0x00010000 0 0 0 0>;
+	};
+};
+
+&switch_ports {
+	port@0 {
+		reg = <0>;
+		label = "enacq";
+	};
+
+	port@1 {
+		reg = <1>;
+		label = "eneport1";
+	};
+
+	port@2 {
+		reg = <2>;
+		label = "enix";
+	};
+
+	port@3 {
+		reg = <3>;
+		label = "enid";
+	};
+
+	port@4 {
+		reg = <4>;
+		label = "cpu";
+		ethernet = <&switch_nic>;
+	};
+
+	port@5 {
+		reg = <5>;
+		label = "enembc";
+
+		/* connected to Ethernet MAC of AT91RM9200 in MII mode */
+		fixed-link {
+			speed = <100>;
+			full-duplex;
+		};
+	};
+};
-- 
2.15.1

[PATCHv1 6/6] ARM: dts: imx6q-b450v3: Add switch port configuration

[Sebastian Reichel]

This adds support for the Marvell switch and names the network
ports according to the labels, that can be found next to the
connectors. The switch is connected to the host system using a
PCI based network card.

The PCI bus configuration has been written using the following
information:

root@b450v3# lspci -tv
-[0000:00]---00.0-[01]----00.0  Intel Corporation I210 Gigabit Network Connection
root@b450v3# lspci -nn
00:00.0 PCI bridge [0604]: Synopsys, Inc. Device [16c3:abcd] (rev 01)
01:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 arch/arm/boot/dts/imx6q-b450v3.dts | 47 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
index 404a93d9596b..693dfa7d751d 100644
--- a/arch/arm/boot/dts/imx6q-b450v3.dts
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -112,3 +112,50 @@
                 line-name = "PCA9539-P07";
         };
 };
+
+&pci_root {
+	/* Intel Corporation I210 Gigabit Network Connection */
+	switch_nic: ethernet@3,0 {
+		compatible = "pci8086,1533";
+		reg = <0x00010000 0 0 0 0>;
+	};
+};
+
+&switch_ports {
+	port@0 {
+		reg = <0>;
+		label = "enacq";
+	};
+
+	port@1 {
+		reg = <1>;
+		label = "eneport1";
+	};
+
+	port@2 {
+		reg = <2>;
+		label = "enix";
+	};
+
+	port@3 {
+		reg = <3>;
+		label = "enid";
+	};
+
+	port@4 {
+		reg = <4>;
+		label = "cpu";
+		ethernet = <&switch_nic>;
+	};
+
+	port@5 {
+		reg = <5>;
+		label = "enembc";
+
+		/* connected to Ethernet MAC of AT91RM9200 in MII mode */
+		fixed-link {
+			speed = <100>;
+			full-duplex;
+		};
+	};
+};
-- 
2.15.1