From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Packham Subject: [PATCH v2 1/3] ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg Date: Thu, 11 Jan 2018 14:59:01 +1300 Message-ID: <20180111015903.11322-2-chris.packham@alliedtelesis.co.nz> References: <20180111015903.11322-1-chris.packham@alliedtelesis.co.nz> Return-path: In-Reply-To: <20180111015903.11322-1-chris.packham@alliedtelesis.co.nz> Sender: linux-kernel-owner@vger.kernel.org To: gregory.clement@free-electrons.com, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, andrew@lunn.ch Cc: jason@lakedaemon.net, sebastian.hesselbarth@gmail.com, linux@armlinux.org.uk, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham , Mark Rutland List-Id: devicetree@vger.kernel.org Enable L2 cache parity and ECC on the db-xc3-24g4xg board so that cache operations are protected and errors can be flagged to the EDAC subsystem. Signed-off-by: Chris Packham --- Changes in v2: - Update commit message arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts index 06fce35d7491..00ca489fc788 100644 --- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts +++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts @@ -70,6 +70,11 @@ }; }; +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + &devbus_bootcs { status = "okay"; -- 2.15.1