[PATCH v2 0/3] ARM: mvebu: dts: updates to enable EDAC

[PATCH v2 0/3] ARM: mvebu: dts: updates to enable EDAC

[Chris Packham]

I've split this off from my earlier series[1] this is just the dts changes that
will enable support for the EDAC series when it lands.

The Armada 38x as well as the 98dx3236 and similar switch chips with integrated
CPUs use the same SDRAM controller block as the Armada XP. The key difference
is the width of the DDR interface.

[1] - https://marc.info/?l=linux-kernel&m=151545124505964&w=2

Changes in v2:
- update commit message
- add labels to dts

Chris Packham (3):
  ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
  ARM: dts: armada-xp: add label to sdram-controller node
  ARM: dts: mvebu: add sdram controller node to Armada-38x

 arch/arm/boot/dts/armada-38x.dtsi             | 5 +++++
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi     | 2 +-
 arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++
 arch/arm/boot/dts/armada-xp.dtsi              | 2 +-
 4 files changed, 12 insertions(+), 2 deletions(-)

-- 
2.15.1

[PATCH v2 1/3] ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg

[Chris Packham]

Enable L2 cache parity and ECC on the db-xc3-24g4xg board so that cache
operations are protected and errors can be flagged to the EDAC
subsystem.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Changes in v2:
- Update commit message

 arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index 06fce35d7491..00ca489fc788 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -70,6 +70,11 @@
 	};
 };
 
+&L2 {
+	arm,parity-enable;
+	marvell,ecc-enable;
+};
+
 &devbus_bootcs {
 	status = "okay";
 
-- 
2.15.1

[PATCH v2 2/3] ARM: dts: armada-xp: add label to sdram-controller node

[Chris Packham]

Add the label "sdramc" to the sdram-controller nodes for the Armada-XP
and 98dx3236 SoCs.

Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
---
Changes in v2:
- New

 arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 2 +-
 arch/arm/boot/dts/armada-xp.dtsi          | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index bdd4c7a45fbf..fe54e9d7cc90 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -127,7 +127,7 @@
 		};
 
 		internal-regs {
-			sdramc@1400 {
+			sdramc: sdramc@1400 {
 				compatible = "marvell,armada-xp-sdram-controller";
 				reg = <0x1400 0x500>;
 			};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index fa1e881266ac..3bb6e5e59fcc 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -73,7 +73,7 @@
 		};
 
 		internal-regs {
-			sdramc@1400 {
+			sdramc: sdramc@1400 {
 				compatible = "marvell,armada-xp-sdram-controller";
 				reg = <0x1400 0x500>;
 			};
-- 
2.15.1

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[PATCH v2 3/3] ARM: dts: mvebu: add sdram controller node to Armada-38x

[Chris Packham]

The Armada-38x uses an SDRAM controller that is compatible with the
Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x
is 32/16). The SDRAM controller registers are the same between the two
SoCs.

Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
---
Changes in v2:
- Add label to sdram-controller node

 arch/arm/boot/dts/armada-38x.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 00ff549d4e39..f9008c4ddd7d 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -138,6 +138,11 @@
 			#size-cells = <1>;
 			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 
+			sdramc: sdramc@1400 {
+				compatible = "marvell,armada-xp-sdram-controller";
+				reg = <0x1400 0x500>;
+			};
+
 			L2: cache-controller@8000 {
 				compatible = "arm,pl310-cache";
 				reg = <0x8000 0x1000>;
-- 
2.15.1

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Re: [PATCH v2 0/3] ARM: mvebu: dts: updates to enable EDAC

[Gregory CLEMENT]

Hi Chris,
 
 On jeu., janv. 11 2018, Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> wrote:

> I've split this off from my earlier series[1] this is just the dts changes that
> will enable support for the EDAC series when it lands.
>
> The Armada 38x as well as the 98dx3236 and similar switch chips with integrated
> CPUs use the same SDRAM controller block as the Armada XP. The key difference
> is the width of the DDR interface.
>
> [1] - https://marc.info/?l=linux-kernel&m=151545124505964&w=2

The series is looks good now. For patch 1 I still wait for that
the "marvell,,ecc-enable" property was accepted before merging it.

So I can either wait for that it was accepted before applying the series,
or just applying patch 2 and 3 for now, as you want.

Thanks,

Gregory


>
> Changes in v2:
> - update commit message
> - add labels to dts
>
> Chris Packham (3):
>   ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
>   ARM: dts: armada-xp: add label to sdram-controller node
>   ARM: dts: mvebu: add sdram controller node to Armada-38x
>
>  arch/arm/boot/dts/armada-38x.dtsi             | 5 +++++
>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi     | 2 +-
>  arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++
>  arch/arm/boot/dts/armada-xp.dtsi              | 2 +-
>  4 files changed, 12 insertions(+), 2 deletions(-)
>
> -- 
> 2.15.1
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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Re: [PATCH v2 0/3] ARM: mvebu: dts: updates to enable EDAC

[Chris Packham]

On 11/01/18 22:14, Gregory CLEMENT wrote:
> Hi Chris,
>   
>   On jeu., janv. 11 2018, Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE1db9wn+61SL@public.gmane.orgz> wrote:
> 
>> I've split this off from my earlier series[1] this is just the dts changes that
>> will enable support for the EDAC series when it lands.
>>
>> The Armada 38x as well as the 98dx3236 and similar switch chips with integrated
>> CPUs use the same SDRAM controller block as the Armada XP. The key difference
>> is the width of the DDR interface.
>>
>> [1] - https://marc.info/?l=linux-kernel&m=151545124505964&w=2
> 
> The series is looks good now. For patch 1 I still wait for that
> the "marvell,,ecc-enable" property was accepted before merging it.
> 
> So I can either wait for that it was accepted before applying the series,
> or just applying patch 2 and 3 for now, as you want.

I'm happy either way. If it's easier for you to keep the 3 patches 
together that's fine by me.

> 
> Thanks,
> 
> Gregory
> 
> 
>>
>> Changes in v2:
>> - update commit message
>> - add labels to dts
>>
>> Chris Packham (3):
>>    ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
>>    ARM: dts: armada-xp: add label to sdram-controller node
>>    ARM: dts: mvebu: add sdram controller node to Armada-38x
>>
>>   arch/arm/boot/dts/armada-38x.dtsi             | 5 +++++
>>   arch/arm/boot/dts/armada-xp-98dx3236.dtsi     | 2 +-
>>   arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++
>>   arch/arm/boot/dts/armada-xp.dtsi              | 2 +-
>>   4 files changed, 12 insertions(+), 2 deletions(-)
>>
>> -- 
>> 2.15.1
>>
> 

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Re: [PATCH v2 0/3] ARM: mvebu: dts: updates to enable EDAC

[Gregory CLEMENT]

Hi Chris,
 
 On jeu., janv. 11 2018, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:

> On 11/01/18 22:14, Gregory CLEMENT wrote:
>> Hi Chris,
>>   
>>   On jeu., janv. 11 2018, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>> 
>>> I've split this off from my earlier series[1] this is just the dts changes that
>>> will enable support for the EDAC series when it lands.
>>>
>>> The Armada 38x as well as the 98dx3236 and similar switch chips with integrated
>>> CPUs use the same SDRAM controller block as the Armada XP. The key difference
>>> is the width of the DDR interface.
>>>
>>> [1] - https://marc.info/?l=linux-kernel&m=151545124505964&w=2
>> 
>> The series is looks good now. For patch 1 I still wait for that
>> the "marvell,,ecc-enable" property was accepted before merging it.
>> 
>> So I can either wait for that it was accepted before applying the series,
>> or just applying patch 2 and 3 for now, as you want.
>
> I'm happy either way. If it's easier for you to keep the 3 patches 
> together that's fine by me.

So I will apply all of them in the same time.


Thanks,

Gregory


>
>> 
>> Thanks,
>> 
>> Gregory
>> 
>> 
>>>
>>> Changes in v2:
>>> - update commit message
>>> - add labels to dts
>>>
>>> Chris Packham (3):
>>>    ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
>>>    ARM: dts: armada-xp: add label to sdram-controller node
>>>    ARM: dts: mvebu: add sdram controller node to Armada-38x
>>>
>>>   arch/arm/boot/dts/armada-38x.dtsi             | 5 +++++
>>>   arch/arm/boot/dts/armada-xp-98dx3236.dtsi     | 2 +-
>>>   arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++
>>>   arch/arm/boot/dts/armada-xp.dtsi              | 2 +-
>>>   4 files changed, 12 insertions(+), 2 deletions(-)
>>>
>>> -- 
>>> 2.15.1
>>>
>> 
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com