From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rask Ingemann Lambertsen Subject: Re: [RFC PATCH 8/9] ARM: dts: suniv: add initial DTSI file for suniv and F1C100s Date: Sun, 21 Jan 2018 12:03:19 +0100 Message-ID: <20180121110319.GD3421@localhost> References: <20180119231735.61504-1-icenowy@aosc.io> <20180119231735.61504-9-icenowy@aosc.io> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20180119231735.61504-9-icenowy@aosc.io> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Icenowy Zheng Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, Marc Zyngier , Linus Walleij , Daniel Lezcano , Russell King , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Chen-Yu Tsai , Maxime Ripard , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org On Sat, Jan 20, 2018 at 07:17:34AM +0800, Icenowy Zheng wrote: > As we have the support for suniv pin controller and CCU now, add a > initial DTSI for it. > > F1C100s is one product with the suniv die, which has a 32MiB co-packaged > DDR1 DRAM chip. As there's nothing special for it, add a dummy DTSI file > for it. [...] > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index d0381e9caf21..b877e0bf1823 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -972,6 +972,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > dtb-$(CONFIG_MACH_SUN9I) += \ > sun9i-a80-optimus.dtb \ > sun9i-a80-cubieboard4.dtb > +dtb-$(CONFIG_MACH_SUNIV) += \ > + suniv-f1c100s-licheepi-nano.dtb > dtb-$(CONFIG_ARCH_TANGO) += \ > tango4-vantage-1172.dtb > dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ The hunk above should go with your patch "[RFC PATCH 9/9] ARM: suniv: f1c100s: add device tree for Lichee Pi Nano" instead. -- Rask Ingemann Lambertsen