From mboxrd@z Thu Jan  1 00:00:00 1970
From: David Miller <davem@davemloft.net>
Subject: Re: [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT
 pin muxing option
Date: Wed, 14 Feb 2018 15:33:57 -0500 (EST)
Message-ID: <20180214.153357.1060464426282681843.davem@davemloft.net>
References: <1518624432-15110-1-git-send-email-d.schultz@phytec.de>
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From: Daniel Schultz <d.schultz@phytec.de>
Date: Wed, 14 Feb 2018 17:07:11 +0100

> From: Wadim Egorov <w.egorov@phytec.de>
> 
> The DP83867 has a muxing option for the CLK_OUT pin. It is possible
> to set CLK_OUT for different channels.
> Create a binding to select a specific clock for CLK_OUT pin.
> 
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
> Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
> ---
> Changes:
> 	v2:
> 	  Added check if clk_output_sel has a valid value
> 	  Only write the clock ouput register if a musing is desired
> 	v3:
> 	  -

Applied to net-next.