From: James Hogan <jhogan@kernel.org>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH v3 1/8] dt-bindings: mips: Add bindings for Microsemi SoCs
Date: Wed, 14 Feb 2018 16:38:39 +0000 [thread overview]
Message-ID: <20180214163838.GB3986@saruman> (raw)
In-Reply-To: <20180116101240.5393-2-alexandre.belloni@free-electrons.com>
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On Tue, Jan 16, 2018 at 11:12:33AM +0100, Alexandre Belloni wrote:
> +o CPU system control:
> +
> +The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
> +the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
> +endianess, CPU bus control, CPU status.
nit: checkpatch suggests endianess should be spelt endianness
Cheers
James
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next prev parent reply other threads:[~2018-02-14 16:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-16 10:12 [PATCH v3 0/8] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni
2018-01-16 10:12 ` [PATCH v3 1/8] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni
[not found] ` <20180116101240.5393-2-alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2018-01-19 19:23 ` Rob Herring
2018-02-14 16:38 ` James Hogan [this message]
2018-01-16 10:12 ` [PATCH v3 2/8] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni
[not found] ` <20180116101240.5393-3-alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2018-01-20 0:34 ` Rob Herring
2018-02-08 22:32 ` Sebastian Reichel
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