From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Burton Subject: [PATCH v5 03/14] dt-bindings: net: Document Intel pch_gbe binding Date: Sat, 17 Feb 2018 12:10:26 -0800 Message-ID: <20180217201037.3006-4-paul.burton@mips.com> References: <20180217201037.3006-1-paul.burton@mips.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20180217201037.3006-1-paul.burton@mips.com> Sender: netdev-owner@vger.kernel.org To: netdev@vger.kernel.org Cc: Hassan Naveed , Matt Redfearn , "David S . Miller" , linux-mips@linux-mips.org, Paul Burton , Mark Rutland , Rob Herring , devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org Introduce documentation for a device tree binding for the Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) device. Although this is a PCIe device & thus largely auto-detectable, this binding will be used to provide the driver with the PHY reset GPIO. Signed-off-by: Paul Burton Cc: David S. Miller Cc: Mark Rutland Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org --- Changes in v5: - Use standard gpio & ethernet node names in example. - Remove bus number from example unit addresses. Changes in v4: None Changes in v3: - New patch. Changes in v2: None Documentation/devicetree/bindings/net/pch_gbe.txt | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt diff --git a/Documentation/devicetree/bindings/net/pch_gbe.txt b/Documentation/devicetree/bindings/net/pch_gbe.txt new file mode 100644 index 000000000000..cff2687e6e75 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pch_gbe.txt @@ -0,0 +1,25 @@ +Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) + +Required properties: +- compatible: Should be the PCI vendor & device ID, eg. "pci8086,8802". +- reg: Should be a PCI device number as specified by the PCI bus + binding to IEEE Std 1275-1994. +- phy-reset-gpios: Should be a GPIO list containing a single GPIO that + resets the attached PHY when active. + +Example: + + ethernet@0,1 { + compatible = "pci8086,8802"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 + GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: gpio@0,2 { + compatible = "pci8086,8803"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; -- 2.16.1