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* [PATCH v5 03/14] dt-bindings: net: Document Intel pch_gbe binding
       [not found] <20180217201037.3006-1-paul.burton@mips.com>
@ 2018-02-17 20:10 ` Paul Burton
       [not found]   ` <20180217201037.3006-4-paul.burton-8NJIiSa5LzA@public.gmane.org>
  0 siblings, 1 reply; 2+ messages in thread
From: Paul Burton @ 2018-02-17 20:10 UTC (permalink / raw)
  To: netdev
  Cc: Hassan Naveed, Matt Redfearn, David S . Miller, linux-mips,
	Paul Burton, Mark Rutland, Rob Herring, devicetree

Introduce documentation for a device tree binding for the Intel Platform
Controller Hub (PCH) GigaBit Ethernet (GBE) device. Although this is a
PCIe device & thus largely auto-detectable, this binding will be used to
provide the driver with the PHY reset GPIO.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5:
- Use standard gpio & ethernet node names in example.
- Remove bus number from example unit addresses.

Changes in v4: None
Changes in v3:
- New patch.

Changes in v2: None

 Documentation/devicetree/bindings/net/pch_gbe.txt | 25 +++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt

diff --git a/Documentation/devicetree/bindings/net/pch_gbe.txt b/Documentation/devicetree/bindings/net/pch_gbe.txt
new file mode 100644
index 000000000000..cff2687e6e75
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pch_gbe.txt
@@ -0,0 +1,25 @@
+Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE)
+
+Required properties:
+- compatible:		Should be the PCI vendor & device ID, eg. "pci8086,8802".
+- reg:			Should be a PCI device number as specified by the PCI bus
+			binding to IEEE Std 1275-1994.
+- phy-reset-gpios:	Should be a GPIO list containing a single GPIO that
+			resets the attached PHY when active.
+
+Example:
+
+	ethernet@0,1 {
+		compatible = "pci8086,8802";
+		reg = <0x00020100 0 0 0 0>;
+		phy-reset-gpios = <&eg20t_gpio 6
+				   GPIO_ACTIVE_LOW>;
+	};
+
+	eg20t_gpio: gpio@0,2 {
+		compatible = "pci8086,8803";
+		reg = <0x00020200 0 0 0 0>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
-- 
2.16.1

^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH v5 03/14] dt-bindings: net: Document Intel pch_gbe binding
       [not found]   ` <20180217201037.3006-4-paul.burton-8NJIiSa5LzA@public.gmane.org>
@ 2018-02-17 22:32     ` Andrew Lunn
  0 siblings, 0 replies; 2+ messages in thread
From: Andrew Lunn @ 2018-02-17 22:32 UTC (permalink / raw)
  To: Paul Burton
  Cc: netdev-u79uwXL29TY76Z2rM5mHXA, Hassan Naveed, Matt Redfearn,
	David S . Miller, linux-mips-6z/3iImG2C8G8FEW9MqTrA, Mark Rutland,
	Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA

> @@ -0,0 +1,25 @@
> +Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE)
> +
> +Required properties:
> +- compatible:		Should be the PCI vendor & device ID, eg. "pci8086,8802".
> +- reg:			Should be a PCI device number as specified by the PCI bus
> +			binding to IEEE Std 1275-1994.
> +- phy-reset-gpios:	Should be a GPIO list containing a single GPIO that
> +			resets the attached PHY when active.
> +

Hi Paul

Please see Documentation/devicetree/bindings/net/phy.txt. In
particular:

reset-gpios: The GPIO phandle and specifier for the PHY reset signal.

You should be conforming to the existing binding.

   Andrew
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^ permalink raw reply	[flat|nested] 2+ messages in thread

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     [not found] <20180217201037.3006-1-paul.burton@mips.com>
2018-02-17 20:10 ` [PATCH v5 03/14] dt-bindings: net: Document Intel pch_gbe binding Paul Burton
     [not found]   ` <20180217201037.3006-4-paul.burton-8NJIiSa5LzA@public.gmane.org>
2018-02-17 22:32     ` Andrew Lunn

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