[PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

[PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

[Alexandre Belloni]

Add a device tree include file for the Microsemi Ocelot SoC.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 arch/mips/boot/dts/Makefile         |   1 +
 arch/mips/boot/dts/mscc/Makefile    |   1 +
 arch/mips/boot/dts/mscc/ocelot.dtsi | 117 ++++++++++++++++++++++++++++++++++++
 3 files changed, 119 insertions(+)
 create mode 100644 arch/mips/boot/dts/mscc/Makefile
 create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi

diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index e2c6f131c8eb..1e79cab8e269 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y	+= cavium-octeon
 subdir-y	+= img
 subdir-y	+= ingenic
 subdir-y	+= lantiq
+subdir-y	+= mscc
 subdir-y	+= mti
 subdir-y	+= netlogic
 subdir-y	+= ni
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
new file mode 100644
index 000000000000..dd08e63a10ba
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -0,0 +1 @@
+obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
new file mode 100644
index 000000000000..8c3210577410
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -0,0 +1,117 @@
+//SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "mscc,ocelot";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "mips,mips24KEc";
+			device_type = "cpu";
+			clocks = <&cpu_clk>;
+			reg = <0>;
+		};
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	cpuintc: interrupt-controller@0 {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "mti,cpu-interrupt-controller";
+	};
+
+	cpu_clk: cpu-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <500000000>;
+	};
+
+	ahb_clk: ahb-clk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&cpu_clk>;
+		clock-div = <2>;
+		clock-mult = <1>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x70000000 0x2000000>;
+
+		interrupt-parent = <&intc>;
+
+		cpu_ctrl: syscon@0 {
+			compatible = "mscc,ocelot-cpu-syscon", "syscon";
+			reg = <0x0 0x2c>;
+		};
+
+		intc: interrupt-controller@70 {
+			compatible = "mscc,ocelot-icpu-intr";
+			reg = <0x70 0x70>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupt-parent = <&cpuintc>;
+			interrupts = <2>;
+		};
+
+		uart0: serial@100000 {
+			pinctrl-0 = <&uart_pins>;
+			pinctrl-names = "default";
+			compatible = "ns16550a";
+			reg = <0x100000 0x20>;
+			interrupts = <6>;
+			clocks = <&ahb_clk>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+
+			status = "disabled";
+		};
+
+		uart2: serial@100800 {
+			pinctrl-0 = <&uart2_pins>;
+			pinctrl-names = "default";
+			compatible = "ns16550a";
+			reg = <0x100800 0x20>;
+			interrupts = <7>;
+			clocks = <&ahb_clk>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+
+			status = "disabled";
+		};
+
+		reset@1070008 {
+			compatible = "mscc,ocelot-chip-reset";
+			reg = <0x1070008 0x4>;
+		};
+
+		gpio: pinctrl@1070034 {
+			compatible = "mscc,ocelot-pinctrl";
+			reg = <0x1070034 0x68>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&gpio 0 0 22>;
+
+			uart_pins: uart-pins {
+				pins = "GPIO_6", "GPIO_7";
+				function = "uart";
+			};
+
+			uart2_pins: uart2-pins {
+				pins = "GPIO_12", "GPIO_13";
+				function = "uart2";
+			};
+		};
+	};
+};
-- 
2.16.2

[PATCH v5 3/5] MIPS: mscc: add ocelot PCB123 device tree

[Alexandre Belloni]

Add a device tree for the Microsemi Ocelot PCB123 evaluation board.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 arch/mips/boot/dts/mscc/Makefile          |  2 ++
 arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 27 +++++++++++++++++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb123.dts

diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
index dd08e63a10ba..c51164537c02 100644
--- a/arch/mips/boot/dts/mscc/Makefile
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -1 +1,3 @@
+dtb-$(CONFIG_LEGACY_BOARD_OCELOT)	+= ocelot_pcb123.dtb
+
 obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
new file mode 100644
index 000000000000..b4e3860c6cf4
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -0,0 +1,27 @@
+//SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/dts-v1/;
+
+#include "ocelot.dtsi"
+
+/ {
+	compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0e000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
-- 
2.16.2

Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

[James Hogan]

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On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote:
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> new file mode 100644
> index 000000000000..8c3210577410
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -0,0 +1,117 @@
> +//SPDX-License-Identifier: (GPL-2.0 OR MIT)

Niggle: there should be a space after // for consistency with other
files. Same in patch 3.

Cheers
James

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Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

[Alexandre Belloni]

On 07/03/2018 at 15:17:56 +0000, James Hogan wrote:
> On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote:
> > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> > new file mode 100644
> > index 000000000000..8c3210577410
> > --- /dev/null
> > +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> > @@ -0,0 +1,117 @@
> > +//SPDX-License-Identifier: (GPL-2.0 OR MIT)
> 
> Niggle: there should be a space after // for consistency with other
> files. Same in patch 3.
> 

Ah, yes...

If that is the only thing left, I can resend right away


-- 
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

[James Hogan]

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On Wed, Mar 07, 2018 at 04:27:51PM +0100, Alexandre Belloni wrote:
> On 07/03/2018 at 15:17:56 +0000, James Hogan wrote:
> > On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote:
> > > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> > > new file mode 100644
> > > index 000000000000..8c3210577410
> > > --- /dev/null
> > > +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> > > @@ -0,0 +1,117 @@
> > > +//SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > 
> > Niggle: there should be a space after // for consistency with other
> > files. Same in patch 3.
> > 
> 
> Ah, yes...
> 
> If that is the only thing left, I can resend right away

There are a couple of irqchip patches from v2 which have gone from the
latest versions:
https://patchwork.linux-mips.org/project/linux-mips/list/?series=568

and the vendor prefix too from v4:
https://patchwork.linux-mips.org/project/linux-mips/list/?series=856

I presume they're all still relevant. Were you expecting the irqchip
ones to go through MIPS too? We'd need an ack from the irqchip folk if
so.

Cheers
James

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Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

[Alexandre Belloni]

On 07/03/2018 at 15:56:07 +0000, James Hogan wrote:
> On Wed, Mar 07, 2018 at 04:27:51PM +0100, Alexandre Belloni wrote:
> > On 07/03/2018 at 15:17:56 +0000, James Hogan wrote:
> > > On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote:
> > > > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> > > > new file mode 100644
> > > > index 000000000000..8c3210577410
> > > > --- /dev/null
> > > > +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> > > > @@ -0,0 +1,117 @@
> > > > +//SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > 
> > > Niggle: there should be a space after // for consistency with other
> > > files. Same in patch 3.
> > > 
> > 
> > Ah, yes...
> > 
> > If that is the only thing left, I can resend right away
> 
> There are a couple of irqchip patches from v2 which have gone from the
> latest versions:
> https://patchwork.linux-mips.org/project/linux-mips/list/?series=568
> 

I'll get those through the irqchip tree.

> and the vendor prefix too from v4:
> https://patchwork.linux-mips.org/project/linux-mips/list/?series=856
> 

My mistake, I prepared my series from that patch, excluded instead of
from that patch, included.

> I presume they're all still relevant. Were you expecting the irqchip
> ones to go through MIPS too? We'd need an ack from the irqchip folk if
> so.
> 
> Cheers
> James



-- 
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

[Rob Herring]

On Tue, Mar 6, 2018 at 6:16 AM, Alexandre Belloni
<alexandre.belloni@bootlin.com> wrote:
> Add a device tree include file for the Microsemi Ocelot SoC.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
>  arch/mips/boot/dts/Makefile         |   1 +
>  arch/mips/boot/dts/mscc/Makefile    |   1 +
>  arch/mips/boot/dts/mscc/ocelot.dtsi | 117 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 119 insertions(+)
>  create mode 100644 arch/mips/boot/dts/mscc/Makefile
>  create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi
>
> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> index e2c6f131c8eb..1e79cab8e269 100644
> --- a/arch/mips/boot/dts/Makefile
> +++ b/arch/mips/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y        += cavium-octeon
>  subdir-y       += img
>  subdir-y       += ingenic
>  subdir-y       += lantiq
> +subdir-y       += mscc
>  subdir-y       += mti
>  subdir-y       += netlogic
>  subdir-y       += ni
> diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
> new file mode 100644
> index 000000000000..dd08e63a10ba
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/Makefile
> @@ -0,0 +1 @@
> +obj-y                          += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> new file mode 100644
> index 000000000000..8c3210577410
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -0,0 +1,117 @@
> +//SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2017 Microsemi Corporation */
> +
> +/ {
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +       compatible = "mscc,ocelot";
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu@0 {
> +                       compatible = "mips,mips24KEc";
> +                       device_type = "cpu";
> +                       clocks = <&cpu_clk>;
> +                       reg = <0>;
> +               };
> +       };
> +
> +       aliases {
> +               serial0 = &uart0;
> +       };
> +
> +       cpuintc: interrupt-controller@0 {

Please compile with W=1 and fix any issues like this one which is a
unit-address without a reg property. Drop the unit-address.

> +               #address-cells = <0>;
> +               #interrupt-cells = <1>;
> +               interrupt-controller;
> +               compatible = "mti,cpu-interrupt-controller";

MIPS DT W=1 warnings (was Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi)

[James Hogan]

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Hi Rob,

On Wed, Mar 07, 2018 at 10:08:28AM -0600, Rob Herring wrote:
> Please compile with W=1 and fix any issues like this one which is a
> unit-address without a reg property. Drop the unit-address.

I was just giving the BMIPS W=1 DT warnings a look, and a few look
spurious. I'd value your opinion on their legitimacy (its hard to care
about W=1 if spurious or seemingly pedantic warnings are going to be
common). e.g.


1)
arch/mips/boot/dts/brcm/bcm9ejtagprb.dtb: Warning (unit_address_vs_reg): Node /ubus/syscon-reboot@10000068 has a unit name, but no reg property          

due to:

periph_cntl: syscon@fff8c000 {
	compatible = "syscon";
	reg = <0xfff8c000 0xc>;
	native-endian;
};

reboot: syscon-reboot@fff8c008 {
	compatible = "syscon-reboot";
	regmap = <&periph_cntl>;
	offset = <0x8>;
	mask = <0x1>;
};

That doesn't seem to take regmap into account. Would you strictly drop
the unit-address in this case, or is there a way the DT compiler can be
fixed (i presume offset and mask are binding specific, so the best it
could do is probably to allow the unit-address due to the regmap without
checking the actual address)?


2)
arch/mips/boot/dts/brcm/bcm9ejtagprb.dtb: Warning (simple_bus_reg): Node /ubus/syscon-reboot@10000068 missing or empty reg/ranges property

Same code as above. Should syscon-reboot be outside of the simple-bus
that both nodes are in, or is it fine there? There's a similar warning
from a DTS which has a syscon property instead of regmap.


3)
arch/mips/boot/dts/brcm/bcm97425svmb.dtb: Warning (simple_bus_reg): Node /rdb@10000000/spi@41c000 simple-bus unit address format error, expected "419920"

qspi: spi@41c000 {
	#address-cells = <0x1>;
	#size-cells = <0x0>;
	compatible = "brcm,spi-bcm-qspi",
		     "brcm,spi-brcmstb-qspi";
	clocks = <&upg_clk>;
	reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
	reg-names = "cs_reg", "hif_mspi", "bspi";
	...

Well 41c000 is one of the reg entries, just not the first. I presume
bspi is the "main" one, perhaps that should come first since we have
reg-names, but even that could potentially confuse driver code if it
didn't find reg resources by name (in this case it does appear to, so
perhaps that would fine)?


Thanks
James

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