From: Weiyi Lu <weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
To: Matthias Brugger
<matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Mike Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
Weiyi Lu <weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Fan Chen <fan.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: [PATCH v2 3/5] dt-bindings: clock: add clocks for MT2712
Date: Mon, 12 Mar 2018 15:03:40 +0800 [thread overview]
Message-ID: <20180312070342.4335-5-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <20180312070342.4335-1-weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu <weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
include/dt-bindings/clock/mt2712-clk.h | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
index 48a8e797a617..76265836a1e1 100644
--- a/include/dt-bindings/clock/mt2712-clk.h
+++ b/include/dt-bindings/clock/mt2712-clk.h
@@ -222,7 +222,13 @@
#define CLK_TOP_APLL_DIV_PDN5 183
#define CLK_TOP_APLL_DIV_PDN6 184
#define CLK_TOP_APLL_DIV_PDN7 185
-#define CLK_TOP_NR_CLK 186
+#define CLK_TOP_APLL1_D3 186
+#define CLK_TOP_APLL1_REF_SEL 187
+#define CLK_TOP_APLL2_REF_SEL 188
+#define CLK_TOP_NFI2X_EN 189
+#define CLK_TOP_NFIECC_EN 190
+#define CLK_TOP_NFI1X_CK_EN 191
+#define CLK_TOP_NR_CLK 192
/* INFRACFG */
@@ -281,7 +287,9 @@
#define CLK_PERI_MSDC30_3_EN 41
#define CLK_PERI_MSDC50_0_HCLK_EN 42
#define CLK_PERI_MSDC50_3_HCLK_EN 43
-#define CLK_PERI_NR_CLK 44
+#define CLK_PERI_MSDC30_0_QTR_EN 44
+#define CLK_PERI_MSDC30_3_QTR_EN 45
+#define CLK_PERI_NR_CLK 46
/* MCUCFG */
--
2.12.5
next prev parent reply other threads:[~2018-03-12 7:03 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-12 7:03 [PATCH v2 0/5] update Mediatek MT2712 clock and scpsys support Weiyi Lu
2018-03-12 7:03 ` Weiyi Lu
2018-03-12 7:03 ` [PATCH v2 1/5] dt-bindings: soc: update MT2712 power dt-bindings Weiyi Lu
2018-03-19 1:32 ` Matthias Brugger
2018-03-12 7:03 ` [PATCH v2 2/5] soc: mediatek: update power domain data of MT2712 Weiyi Lu
2018-03-19 1:33 ` Matthias Brugger
[not found] ` <20180312070342.4335-1-weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2018-03-12 7:03 ` Weiyi Lu [this message]
2018-03-18 12:48 ` [PATCH v2 3/5] dt-bindings: clock: add clocks for MT2712 Rob Herring
2018-03-19 21:38 ` Stephen Boyd
2018-03-12 7:03 ` [PATCH v2 4/5] arm64: dts: add clock device nodes of MT2712 Weiyi Lu
2018-03-12 7:03 ` [PATCH v2 5/5] clk: mediatek: update clock driver " Weiyi Lu
2018-03-19 21:38 ` Stephen Boyd
2018-03-20 6:07 ` [PATCH v2 0/5] update Mediatek MT2712 clock and scpsys support Weiyi Lu
2018-03-20 7:23 ` Stephen Boyd
2018-03-21 9:11 ` Matthias Brugger
2018-04-17 14:22 ` Matthias Brugger
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