[PATCH 2/5] dt-bindings: usb: add binding for the DWC3 controller on Allwinner SoC

[Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>]

The Allwinner H6 SoC uses DWC3 controller for USB3.

Add its device tree binding document.

Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
 .../bindings/usb/allwinner,dwc3.txt           | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/allwinner,dwc3.txt

diff --git a/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
new file mode 100644
index 000000000000..3f7714636785
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
@@ -0,0 +1,39 @@
+Allwinner SuperSpeed DWC3 USB SoC controller
+
+Required properties:
+- compatible:	should contain "allwinner,sun50i-h6-dwc3" for H6 SoC
+- clocks:	A list of phandle + clock-specifier pairs for the
+		clocks listed in clock-names
+- clock-names:	Should contain the following:
+  "bus"		The bus clock of the DWC3 part
+- resets:	A list of phandle + reset-specifier pairs for the
+		resets listed in reset-names
+- reset-names:	Should contain the following:
+  "bus"		The bus reset of the DWC3 part
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+Phy documentation is provided in the following places:
+Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
+
+Example device nodes:
+	usb3: usb@5200000 {
+		compatible = "allwinner,sun50i-h6-dwc3";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clocks = <&ccu CLK_BUS_XHCI>;
+		clock-names = "bus";
+		resets = <&ccu RST_BUS_XHCI>;
+		reset-names = "bus";
+
+		dwc3: dwc3 {
+			compatible = "snps,dwc3";
+			reg = <0x5200000 0x10000>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usb3phy>;
+			phy-names = "usb3-phy";
+		};
+	};
-- 
2.17.0