From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding Date: Wed, 6 Jun 2018 12:39:03 +0200 Message-ID: <20180606103903.GJ11810@ulmo> References: <20180531221637.6017-1-stefan@agner.ch> <20180531221637.6017-4-stefan@agner.ch> <20180601093025.2817ff30@bbrezillon> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="C7PTD44AewjTsiSV" Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Dmitry Osipenko Cc: Boris Brezillon , Stefan Agner , dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, benjamin.lindqvist@endian.se, pgaikwad@nvidia.com, dev@lynxeye.de, mirza.krak@gmail.com, richard@nod.at, pdeschrijver@nvidia.com, linux-kernel@vger.kernel.org, krzk@kernel.org, jonathanh@nvidia.com, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, marcel@ziswiler.com, miquel.raynal@bootlin.com, linux-tegra@vger.kernel.org List-Id: devicetree@vger.kernel.org --C7PTD44AewjTsiSV Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Jun 05, 2018 at 11:19:14PM +0300, Dmitry Osipenko wrote: > On 01.06.2018 10:30, Boris Brezillon wrote: > > On Fri, 1 Jun 2018 00:16:34 +0200 > > Stefan Agner wrote: > >=20 > >> This adds the devicetree binding for the Tegra 2 NAND flash > >> controller. > >> > >> Signed-off-by: Lucas Stach > >> Signed-off-by: Stefan Agner > >> --- > >> .../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++++++++++++++++++ > >> 1 file changed, 64 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/mtd/nvidia-tegra= 20-nand.txt > >> > >> diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand= =2Etxt b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt > >> new file mode 100644 > >> index 000000000000..5cd984ef046b > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt > >> @@ -0,0 +1,64 @@ > >> +NVIDIA Tegra NAND Flash controller > >> + > >> +Required properties: > >> +- compatible: Must be one of: > >> + - "nvidia,tegra20-nand" > >=20 > > As discussed previously, I prefer "nvidia,tegra20-nand-controller" or > > "nvidia,tegra20-nfc". > >=20 > >> +- reg: MMIO address range > >> +- interrupts: interrupt output of the NFC controller > >> +- clocks: Must contain an entry for each entry in clock-names. > >> + See ../clocks/clock-bindings.txt for details. > >> +- clock-names: Must include the following entries: > >> + - nand > >> +- resets: Must contain an entry for each entry in reset-names. > >> + See ../reset/reset.txt for details. > >> +- reset-names: Must include the following entries: > >> + - nand > >> + > >> +Optional children nodes: > >> +Individual NAND chips are children of the NAND controller node. Curre= ntly > >> +only one NAND chip supported. > >> + > >> +Required children node properties: > >> +- reg: An integer ranging from 1 to 6 representing the CS line to use. > >> + > >> +Optional children node properties: > >> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. Current= ly only > >> + "hw" is supported. > >> +- nand-ecc-algo: string, algorithm of NAND ECC. > >> + Supported values with "hw" ECC mode are: "rs", "bch". > >> +- nand-bus-width : See nand.txt > >> +- nand-on-flash-bbt: See nand.txt > >> +- nand-ecc-strength: integer representing the number of bits to corre= ct > >> + per ECC step (always 512). Supported strength using HW ECC > >> + modes are: > >> + - RS: 4, 6, 8 > >> + - BCH: 4, 8, 14, 16 > >> +- nand-ecc-maximize: See nand.txt > >> +- nand-is-boot-medium: Makes sure only ECC strengths supported by the= boot ROM > >> + are choosen. > >> +- wp-gpios: GPIO specifier for the write protect pin. > >> + > >> +Optional child node of NAND chip nodes: > >> +Partitions: see partition.txt > >> + > >> + Example: > >> + nand@70008000 { > >=20 > > nand-controller@70008000 { > >=20 > >> + compatible =3D "nvidia,tegra20-nand"; > >=20 > > compatible =3D "nvidia,tegra20-nand-controller"; > >=20 > > or > >=20 > > compatible =3D "nvidia,tegra20-nfc"; > >=20 >=20 > Maybe it's just me, but when I'm reading "nfc", my first association is t= he > "Near Field Communication". Probably an explicit > "nvidia,tegra20-nand-controller" variant is more preferable. We don't really use a -controller suffix for any of the other controllers because it is kind of implied. "nfc" is also not something that is ever referred to in the technical documentation. "nvidia,tegra20-nand" would be most consistent with all the rest of Tegra (c.f. "nvidia,tegra*-ahci", "nvidia,tegra*-pci", "nvidia,tegra*-hda", "nvidia,tegra*-gmi", ...). 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