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From: Rob Herring <robh@kernel.org>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Andrew Jeffery <andrew@aj.id.au>,
	devicetree@vger.kernel.org, linux-aspeed@lists.ozlabs.org,
	Joel Stanley <joel@jms.id.au>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/4] dt-bindings: misc: Aspeed coprocessor interrupt controller
Date: Wed, 20 Jun 2018 13:49:37 -0600	[thread overview]
Message-ID: <20180620194937.GA5088@rob-hp-laptop> (raw)
In-Reply-To: <20180618045902.11453-3-benh@kernel.crashing.org>

On Mon, Jun 18, 2018 at 02:59:00PM +1000, Benjamin Herrenschmidt wrote:
> Add the device-tree binding definition for the AST2400
> and AST2500 coprocessor interrupt controller
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>  .../devicetree/bindings/misc/aspeed,cvic.txt  | 35 +++++++++++++++++++
>  1 file changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> 
> diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> new file mode 100644
> index 000000000000..2562e2991e4d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> @@ -0,0 +1,35 @@
> +* Aspeed AST2400 and AST2500 coprocessor interrupt controller
> +
> +This file describes the bindings for the interrupt controller present
> +in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
> +ColdFire coprocessor.
> +
> +It is not a normal interrupt controller and it would be rather
> +inconvenient to create an interrupt tree for it as it somewhat shares
> +some of the same sources as the main ARM interrupt controller but with
> +different numbers.
> +
> +The AST2500 supports a SW generated interrupt
> +
> +Required properties:
> +- reg: address and length of the register for the device.
> +- compatible: "aspeed,cvic" and one of:
> +		"aspeed,ast2400-cvic"
> +	      or
> +		"aspeed,ast2500-cvic"
> +
> +- valid-sources: One cell, bitmap of supported sources for the implementation

aspeed,valid-sources

This could use a better description. I thought this was which bits to 
use for s/w irq, but then I read the next property...

Alternatively, why can't this be implied by the compatible?

> +
> +Optional properties;
> +- copro-sw-interrupts: List of interrupt numbers that can be used as
> +		       SW interrupts from the ARM to the coprocessor.
> +		       (AST2500 only)
> +
> +Example:
> +
> +	cvic: copro-interrupt-controller@1e6c2000 {
> +		compatible = "aspeed,ast2500-cvic";
> +		valid-sources = <0xffffffff>;
> +		copro-sw-interrupts = <1>;
> +		reg = <0x1e6c2000 0x80>;
> +	};
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2018-06-20 19:49 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-18  4:58 [PATCH v2 0/4] arm: dts: Aspeed SoC device-tree update Benjamin Herrenschmidt
2018-06-18  4:58 ` [PATCH v2 1/4] arm: dts: Fix error in Aspeed OpenPower Romulus device-tree Benjamin Herrenschmidt
2018-06-18  5:16   ` Benjamin Herrenschmidt
2018-06-18  4:59 ` [PATCH v2 2/4] dt-bindings: misc: Aspeed coprocessor interrupt controller Benjamin Herrenschmidt
2018-06-19  6:56   ` Joel Stanley
2018-06-19  6:58     ` Benjamin Herrenschmidt
2018-06-20 19:49   ` Rob Herring [this message]
2018-06-20 23:05     ` Benjamin Herrenschmidt
2018-06-18  4:59 ` [PATCH v2 3/4] arm: dts: Update AST2500 device-tree Benjamin Herrenschmidt
2018-06-18  4:59 ` [PATCH v2 4/4] arm: dts: Update AST2400 device-tree Benjamin Herrenschmidt

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