* [PATCH 10/25] dt-bindings: PCI: qcom,ar7100: adds binding doc
[not found] <20180625171549.4618-1-john@phrozen.org>
@ 2018-06-25 17:15 ` John Crispin
2018-06-25 18:06 ` Sergei Shtylyov
2018-07-03 22:05 ` Rob Herring
2018-06-25 17:15 ` [PATCH 12/25] dt-bindings: PCI: qcom,ar7240: " John Crispin
1 sibling, 2 replies; 6+ messages in thread
From: John Crispin @ 2018-06-25 17:15 UTC (permalink / raw)
To: James Hogan, Ralf Baechle
Cc: linux-mips, John Crispin, Rob Herring, devicetree
With the driver being converted from platform_data to pure OF, we need to
also add some docs.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: John Crispin <john@phrozen.org>
---
.../devicetree/bindings/pci/qcom,ar7100-pci.txt | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
new file mode 100644
index 000000000000..97be7b0c4cf9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
@@ -0,0 +1,36 @@
+* Qualcomm Atheros AR7100 PCI express root complex
+
+Required properties:
+- compatible: should contain "qcom,ar7100-pci" to identify the core.
+- reg: Should contain the register ranges as listed in the reg-names property.
+- reg-names: Definition: Must include the following entries
+ - "cfg_base" IO Memory
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- ranges: ranges for the PCI memory and I/O regions
+- interrupt-map-mask and interrupt-map: standard PCI
+ properties to define the mapping of the PCIe interface to interrupt
+ numbers.
+- #interrupt-cells: set to <1>
+- interrupt-parent: phandle to the MIPS IRQ controller
+- interrupt-controller: define to enable the builtin IRQ cascade.
+
+* Example for ar7100
+ pcie0: pcie-controller@180c0000 {
+ compatible = "qca,ar7100-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ reg = <0x17010000 0x100>;
+ reg-names = "cfg_base";
+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-map-mask = <0 0 0 1>;
+ interrupt-map = <0 0 0 0 &pcie0 0>;
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 12/25] dt-bindings: PCI: qcom,ar7240: adds binding doc
[not found] <20180625171549.4618-1-john@phrozen.org>
2018-06-25 17:15 ` [PATCH 10/25] dt-bindings: PCI: qcom,ar7100: adds binding doc John Crispin
@ 2018-06-25 17:15 ` John Crispin
2018-07-03 22:08 ` Rob Herring
1 sibling, 1 reply; 6+ messages in thread
From: John Crispin @ 2018-06-25 17:15 UTC (permalink / raw)
To: James Hogan, Ralf Baechle
Cc: linux-mips, John Crispin, Rob Herring, devicetree
With the driver being converted from platform_data to pure OF, we need to
also add some docs.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: John Crispin <john@phrozen.org>
---
.../devicetree/bindings/pci/qcom,ar7240-pci.txt | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
new file mode 100644
index 000000000000..7f6ca8a0f859
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
@@ -0,0 +1,40 @@
+* Qualcomm Atheros AR724X PCI express root complex
+
+Required properties:
+- compatible: should contain "qcom,ar7240-pci" to identify the core.
+- reg: Should contain the register ranges as listed in the reg-names property.
+- reg-names: Definition: Must include the following entries
+ - "crp_base" Configuration registers
+ - "ctrl_base" Control registers
+ - "cfg_base" IO Memory
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- ranges: ranges for the PCI memory and I/O regions
+- interrupt-map-mask and interrupt-map: standard PCI
+ properties to define the mapping of the PCIe interface to interrupt
+ numbers.
+- #interrupt-cells: set to <1>
+- interrupt-parent: phandle to the MIPS IRQ controller
+- interrupt-controller: define to enable the builtin IRQ cascade.
+
+* Example for qca9557
+ pcie0: pcie-controller@180c0000 {
+ compatible = "qcom,ar7240-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ reg = <0x180c0000 0x1000>,
+ <0x180f0000 0x100>,
+ <0x14000000 0x1000>;
+ reg-names = "crp_base", "ctrl_base", "cfg_base";
+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000
+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
+ interrupt-parent = <&intc2>;
+ interrupts = <1>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-map-mask = <0 0 0 1>;
+ interrupt-map = <0 0 0 0 &pcie0 0>;
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 10/25] dt-bindings: PCI: qcom,ar7100: adds binding doc
2018-06-25 17:15 ` [PATCH 10/25] dt-bindings: PCI: qcom,ar7100: adds binding doc John Crispin
@ 2018-06-25 18:06 ` Sergei Shtylyov
2018-06-26 7:13 ` John Crispin
2018-07-03 22:05 ` Rob Herring
1 sibling, 1 reply; 6+ messages in thread
From: Sergei Shtylyov @ 2018-06-25 18:06 UTC (permalink / raw)
To: John Crispin, James Hogan, Ralf Baechle
Cc: linux-mips, Rob Herring, devicetree
On 06/25/2018 08:15 PM, John Crispin wrote:
> With the driver being converted from platform_data to pure OF, we need to
> also add some docs.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: John Crispin <john@phrozen.org>
> ---
> .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
> new file mode 100644
> index 000000000000..97be7b0c4cf9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
> @@ -0,0 +1,36 @@
> +* Qualcomm Atheros AR7100 PCI express root complex
> +
> +Required properties:
> +- compatible: should contain "qcom,ar7100-pci" to identify the core.
> +- reg: Should contain the register ranges as listed in the reg-names property.
> +- reg-names: Definition: Must include the following entries
> + - "cfg_base" IO Memory
> +- #address-cells: set to <3>
> +- #size-cells: set to <2>
> +- ranges: ranges for the PCI memory and I/O regions
> +- interrupt-map-mask and interrupt-map: standard PCI
> + properties to define the mapping of the PCIe interface to interrupt
> + numbers.
> +- #interrupt-cells: set to <1>
> +- interrupt-parent: phandle to the MIPS IRQ controller
Never a required prop, can be "inherited" from the parent node.
> +- interrupt-controller: define to enable the builtin IRQ cascade.
> +
> +* Example for ar7100
> + pcie0: pcie-controller@180c0000 {
Name it just "pcie@180c0000", please.
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 10/25] dt-bindings: PCI: qcom,ar7100: adds binding doc
2018-06-25 18:06 ` Sergei Shtylyov
@ 2018-06-26 7:13 ` John Crispin
0 siblings, 0 replies; 6+ messages in thread
From: John Crispin @ 2018-06-26 7:13 UTC (permalink / raw)
To: Sergei Shtylyov, James Hogan, Ralf Baechle
Cc: linux-mips, Rob Herring, devicetree
On 25/06/18 20:06, Sergei Shtylyov wrote:
> On 06/25/2018 08:15 PM, John Crispin wrote:
>
>> With the driver being converted from platform_data to pure OF, we need to
>> also add some docs.
>>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: John Crispin <john@phrozen.org>
>> ---
>> .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 36 ++++++++++++++++++++++
>> 1 file changed, 36 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
>> new file mode 100644
>> index 000000000000..97be7b0c4cf9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
>> @@ -0,0 +1,36 @@
>> +* Qualcomm Atheros AR7100 PCI express root complex
>> +
>> +Required properties:
>> +- compatible: should contain "qcom,ar7100-pci" to identify the core.
>> +- reg: Should contain the register ranges as listed in the reg-names property.
>> +- reg-names: Definition: Must include the following entries
>> + - "cfg_base" IO Memory
>> +- #address-cells: set to <3>
>> +- #size-cells: set to <2>
>> +- ranges: ranges for the PCI memory and I/O regions
>> +- interrupt-map-mask and interrupt-map: standard PCI
>> + properties to define the mapping of the PCIe interface to interrupt
>> + numbers.
>> +- #interrupt-cells: set to <1>
>> +- interrupt-parent: phandle to the MIPS IRQ controller
> Never a required prop, can be "inherited" from the parent node.
>
>> +- interrupt-controller: define to enable the builtin IRQ cascade.
>> +
>> +* Example for ar7100
>> + pcie0: pcie-controller@180c0000 {
> Name it just "pcie@180c0000", please.
>
> [...]
>
> MBR, Sergei
>
Thanks, fixed in my local tree, also for the ar7240 doc. I'll wait to
see what other feedback i get before sending a V2
John
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 10/25] dt-bindings: PCI: qcom,ar7100: adds binding doc
2018-06-25 17:15 ` [PATCH 10/25] dt-bindings: PCI: qcom,ar7100: adds binding doc John Crispin
2018-06-25 18:06 ` Sergei Shtylyov
@ 2018-07-03 22:05 ` Rob Herring
1 sibling, 0 replies; 6+ messages in thread
From: Rob Herring @ 2018-07-03 22:05 UTC (permalink / raw)
To: John Crispin; +Cc: James Hogan, Ralf Baechle, linux-mips, devicetree
On Mon, Jun 25, 2018 at 07:15:34PM +0200, John Crispin wrote:
> With the driver being converted from platform_data to pure OF, we need to
> also add some docs.
No need to say "binding" twice in the subject.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: John Crispin <john@phrozen.org>
> ---
> .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
> new file mode 100644
> index 000000000000..97be7b0c4cf9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
> @@ -0,0 +1,36 @@
> +* Qualcomm Atheros AR7100 PCI express root complex
> +
> +Required properties:
> +- compatible: should contain "qcom,ar7100-pci" to identify the core.
> +- reg: Should contain the register ranges as listed in the reg-names property.
> +- reg-names: Definition: Must include the following entries
> + - "cfg_base" IO Memory
> +- #address-cells: set to <3>
> +- #size-cells: set to <2>
> +- ranges: ranges for the PCI memory and I/O regions
> +- interrupt-map-mask and interrupt-map: standard PCI
> + properties to define the mapping of the PCIe interface to interrupt
> + numbers.
> +- #interrupt-cells: set to <1>
> +- interrupt-parent: phandle to the MIPS IRQ controller
You can just omit this. As pointed out it can be inherited from the
parent.
> +- interrupt-controller: define to enable the builtin IRQ cascade.
This is mutually exclusive with interrupt-map. At least of_irq_parse_raw
will never parse interrupt-map if it finds interrupt-controller.
> +
> +* Example for ar7100
> + pcie0: pcie-controller@180c0000 {
pcie@...
Building your dtb with W=1 (or W=12) will tell you this.
> + compatible = "qca,ar7100-pci";
qca or qcom as above?
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0x0>;
> + reg = <0x17010000 0x100>;
> + reg-names = "cfg_base";
> + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
> + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-map-mask = <0 0 0 1>;
> + interrupt-map = <0 0 0 0 &pcie0 0>;
> + };
> --
> 2.11.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 12/25] dt-bindings: PCI: qcom,ar7240: adds binding doc
2018-06-25 17:15 ` [PATCH 12/25] dt-bindings: PCI: qcom,ar7240: " John Crispin
@ 2018-07-03 22:08 ` Rob Herring
0 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2018-07-03 22:08 UTC (permalink / raw)
To: John Crispin; +Cc: James Hogan, Ralf Baechle, linux-mips, devicetree
On Mon, Jun 25, 2018 at 07:15:36PM +0200, John Crispin wrote:
> With the driver being converted from platform_data to pure OF, we need to
> also add some docs.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: John Crispin <john@phrozen.org>
> ---
> .../devicetree/bindings/pci/qcom,ar7240-pci.txt | 40 ++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
> new file mode 100644
> index 000000000000..7f6ca8a0f859
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
> @@ -0,0 +1,40 @@
> +* Qualcomm Atheros AR724X PCI express root complex
> +
> +Required properties:
> +- compatible: should contain "qcom,ar7240-pci" to identify the core.
> +- reg: Should contain the register ranges as listed in the reg-names property.
> +- reg-names: Definition: Must include the following entries
> + - "crp_base" Configuration registers
> + - "ctrl_base" Control registers
> + - "cfg_base" IO Memory
IO or config space? IO space goes in ranges and config space goes
in reg.
Same comments as 7100 below.
> +- #address-cells: set to <3>
> +- #size-cells: set to <2>
> +- ranges: ranges for the PCI memory and I/O regions
> +- interrupt-map-mask and interrupt-map: standard PCI
> + properties to define the mapping of the PCIe interface to interrupt
> + numbers.
> +- #interrupt-cells: set to <1>
> +- interrupt-parent: phandle to the MIPS IRQ controller
> +- interrupt-controller: define to enable the builtin IRQ cascade.
> +
> +* Example for qca9557
> + pcie0: pcie-controller@180c0000 {
> + compatible = "qcom,ar7240-pci";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0x0>;
> + reg = <0x180c0000 0x1000>,
> + <0x180f0000 0x100>,
> + <0x14000000 0x1000>;
> + reg-names = "crp_base", "ctrl_base", "cfg_base";
> + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000
> + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
> + interrupt-parent = <&intc2>;
> + interrupts = <1>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-map-mask = <0 0 0 1>;
> + interrupt-map = <0 0 0 0 &pcie0 0>;
> + };
> --
> 2.11.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
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[not found] <20180625171549.4618-1-john@phrozen.org>
2018-06-25 17:15 ` [PATCH 10/25] dt-bindings: PCI: qcom,ar7100: adds binding doc John Crispin
2018-06-25 18:06 ` Sergei Shtylyov
2018-06-26 7:13 ` John Crispin
2018-07-03 22:05 ` Rob Herring
2018-06-25 17:15 ` [PATCH 12/25] dt-bindings: PCI: qcom,ar7240: " John Crispin
2018-07-03 22:08 ` Rob Herring
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