[PATCH 01/21] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding

[PATCH 01/21] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding

[Sean Paul]

From: Jeykumar Sankaran <jsanka@codeaurora.org>

Adds mdp transfer time to msm dsi binding

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 .../devicetree/bindings/display/msm/dsi.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index 518e9cdf0d4b..d22237a88eae 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -121,6 +121,20 @@ Required properties:
 Optional properties:
 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
   regulator is wanted.
+- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode
+					panels in microseconds. Driver uses this number to adjust
+					the clock rate according to the expected transfer time.
+					Increasing this value would slow down the mdp processing
+					and can result in slower performance.
+					Decreasing this value can speed up the mdp processing,
+					but this can also impact power consumption.
+					As a rule this time should not be higher than the time
+					that would be expected with the processing at the
+					dsi link rate since anyways this would be the maximum
+					transfer time that could be achieved.
+					If ping pong split is enabled, this time should not be higher
+					than two times the dsi link rate time.
+					If the property is not specified, then the default value is 14000 us.
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 [2] Documentation/devicetree/bindings/graph.txt
@@ -171,6 +185,8 @@ Example:
 		qcom,master-dsi;
 		qcom,sync-dual-dsi;
 
+		qcom,mdss-mdp-transfer-time-us = <12000>;
+
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&dsi_active>;
 		pinctrl-1 = <&dsi_suspend>;
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[PATCH 02/21] dt-bindings: clock: Introduce QCOM Display clock bindings

[Sean Paul]

From: Taniya Das <tdas@codeaurora.org>

Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 .../devicetree/bindings/clock/qcom,dispcc.txt | 19 ++++++++
 .../dt-bindings/clock/qcom,dispcc-sdm845.h    | 45 +++++++++++++++++++
 2 files changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc.txt
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sdm845.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt
new file mode 100644
index 000000000000..d639e18d0b85
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt
@@ -0,0 +1,19 @@
+Qualcomm Technologies, Inc. Display Clock Controller Binding
+------------------------------------------------------------
+
+Required properties :
+
+- compatible : shall contain "qcom,sdm845-dispcc"
+- reg : shall contain base register location and length.
+- #clock-cells : from common clock binding, shall contain 1.
+- #reset-cells : from common reset binding, shall contain 1.
+- #power-domain-cells : from generic power domain binding, shall contain 1.
+
+Example:
+	dispcc: clock-controller@af00000 {
+		compatible = "qcom,sdm845-dispcc";
+		reg = <0xaf00000 0x100000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		#power-domain-cells = <1>;
+	};
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
new file mode 100644
index 000000000000..11eed4bc9646
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK					0
+#define DISP_CC_MDSS_AXI_CLK					1
+#define DISP_CC_MDSS_BYTE0_CLK					2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				3
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				4
+#define DISP_CC_MDSS_BYTE1_CLK					5
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				6
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				7
+#define DISP_CC_MDSS_ESC0_CLK					8
+#define DISP_CC_MDSS_ESC0_CLK_SRC				9
+#define DISP_CC_MDSS_ESC1_CLK					10
+#define DISP_CC_MDSS_ESC1_CLK_SRC				11
+#define DISP_CC_MDSS_MDP_CLK					12
+#define DISP_CC_MDSS_MDP_CLK_SRC				13
+#define DISP_CC_MDSS_MDP_LUT_CLK				14
+#define DISP_CC_MDSS_PCLK0_CLK					15
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				16
+#define DISP_CC_MDSS_PCLK1_CLK					17
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				18
+#define DISP_CC_MDSS_ROT_CLK					19
+#define DISP_CC_MDSS_ROT_CLK_SRC				20
+#define DISP_CC_MDSS_RSCC_AHB_CLK				21
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				22
+#define DISP_CC_MDSS_VSYNC_CLK					23
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				24
+#define DISP_CC_PLL0						25
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				26
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				27
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_RSCC_BCR					0
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC						0
+
+#endif
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[PATCH 19/21] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU

[Sean Paul]

From: Jeykumar Sankaran <jsanka@codeaurora.org>

Adds bindings for Snapdragon 845 display processing unit

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 .../devicetree/bindings/display/msm/dpu.txt   | 128 ++++++++++++++++++
 1 file changed, 128 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt

diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt
new file mode 100644
index 000000000000..080fb77624a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -0,0 +1,128 @@
+Qualcomm Technologies, Inc. DPU KMS
+
+Description:
+
+Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+sub-blocks like DPU display controller, DSI and DP interfaces etc.
+The DPU display controller is found in SDM845 SoC.
+
+MDSS:
+Required properties:
+- compatible: "qcom,dpu-mdss"
+- reg: physical base address and length of contoller's registers.
+- reg-names: register region names. The following region is required:
+  * "mdss_phys"
+- power-domains: a power domain consumer specifier according to
+  Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: list of phandles for clock device nodes needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+  The following clocks are required:
+  * "iface"
+  * "bus"
+  * "core"
+- interrupts: interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+  source, should be 1.
+- iommus: phandle of iommu device node.
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
+
+Optional properties:
+- clock-frequency: list of clock frequencies sorted in the same order as the
+  clocks property.
+
+MDP:
+Required properties:
+- compatible: "qcom,dpu"
+- reg: physical base address and length of controller's registers.
+- reg-names : register region names. The following region is required:
+  * "mdp_phys"
+  * "vbif_phys"
+- clocks: list of phandles for clock device nodes needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+  The following clocks are required.
+  * "bus"
+  * "iface"
+  * "core"
+  * "vsync"
+- interrupt-parent: phandle to MDSS block.
+- interrupts: interrupt line from DPU to MDSS.
+- ports: contains the list of output ports from DPU device. These ports connect
+  to interfaces that are external to the DPU hardware, such as DSI, DP etc.
+
+  Each output port contains an endpoint that describes how it is connected to an
+  external interface. These are described by the standard properties documented
+  here:
+	Documentation/devicetree/bindings/graph.txt
+	Documentation/devicetree/bindings/media/video-interfaces.txt
+
+	Port 0 -> DPU_INTF1 (DSI1)
+	Port 1 -> DPU_INTF2 (DSI2)
+
+Optional properties:
+- clock-frequency: list of clock frequencies sorted in the same order as the
+  clocks property.
+
+Example:
+
+	mdss: mdss@ae00000 {
+		compatible = "qcom,dpu-mdss";
+		reg = <0xae00000 0x1000>;
+		reg-names = "mdss_phys";
+
+		power-domains = <&clock_dispcc 0>;
+
+		clocks = <&gcc GCC_DISP_AHB_CLK>,
+			 <&gcc GCC_DISP_AXI_CLK>,
+			 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+		clock-names = "iface", "bus", "core";
+		clock-frequency = <0 0 300000000>;
+
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		iommus = <&apps_iommu 0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		mdss_mdp: mdp@ae01000 {
+			compatible = "qcom,dpu";
+			reg = <0x0ae01000 0x8f000>,
+			      <0x0aeb0000 0x2008>;
+			reg-names = "mdp_phys", "vbif_phys";
+
+			clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+				 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
+				 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+				 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+			clock-names = "iface", "bus", "core", "vsync";
+			clock-frequency = <0 0 300000000 19200000>;
+
+			interrupt-parent = <&mdss>;
+			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dpu_intf1_out: endpoint {
+						remote-endpoint = <&dsi0_in>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dpu_intf2_out: endpoint {
+						remote-endpoint = <&dsi1_in>;
+					};
+				};
+			};
+		};
+	};
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file

[Sean Paul]

Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 194 +++++++++++++++++++++++++++
 1 file changed, 194 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index cdaabeb3c995..339afed856de 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5,6 +5,8 @@
  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -221,6 +223,198 @@
 			#interrupt-cells = <2>;
 		};
 
+		mdss: mdss@ae00000 {
+			compatible = "qcom,dpu-mdss";
+			reg = <0xae00000 0x1000>;
+			reg-names = "mdss_phys";
+
+			power-domains = <&dispcc 0>;
+
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&gcc GCC_DISP_AXI_CLK>,
+				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
+			clock-names = "iface", "bus", "core";
+			clock-frequency = <0 0 300000000>;
+
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			/* iommus = <&apps_iommu 0>; */
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mdss_mdp: mdp@ae01000 {
+				compatible = "qcom,dpu";
+				reg = <0x0ae01000 0x8f000>,
+				      <0x0aeb0000 0x2008>;
+				reg-names = "mdp_phys", "vbif_phys";
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>,
+					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "iface", "bus", "core", "vsync";
+				clock-frequency = <0 0 300000000 19200000>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dpu_intf1_out: endpoint {
+							remote-endpoint = <&dsi0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dpu_intf2_out: endpoint {
+							remote-endpoint = <&dsi1_in>;
+						};
+					};
+				};
+			};
+
+			dsi0: dsi@ae94000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0xae94000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4 0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte_clk",
+					      "byte_intf_clk",
+					      "pixel_clk",
+					      "core_clk",
+					      "iface_clk",
+					      "bus_clk";
+
+				phys = <&dsi0_phy>;
+				phy-names = "dsi-phy";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi0_in: endpoint {
+							remote-endpoint = <&dpu_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi0_phy: dsi-phy@ae94400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0xae94400 0x200>,
+				      <0xae94a00 0x1e0>,
+				      <0xae94600 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_pll",
+					    "dsi_phy_lane";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "iface_clk";
+			};
+
+			dsi1: dsi@ae96000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0xae96000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <5 0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte_clk",
+					      "byte_intf_clk",
+					      "pixel_clk",
+					      "core_clk",
+					      "iface_clk",
+					      "bus_clk";
+
+				phys = <&dsi1_phy>;
+				phy-names = "dsi-phy";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi1_in: endpoint {
+							remote-endpoint = <&dpu_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi1_phy: dsi-phy@ae96400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0xae96400 0x200>,
+				      <0xae96a00 0x10e>,
+				      <0xae96600 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_pll",
+					    "dsi_phy_lane";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "iface_clk";
+			};
+		};
+
+		dispcc: qcom,dispcc@af00000 {
+			compatible = "qcom,sdm845-dispcc";
+			reg = <0xaf00000 0x10000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		spmi_bus: spmi@c440000 {
 			compatible = "qcom,spmi-pmic-arb";
 			reg = <0xc440000 0x1100>,
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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Re: [PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file

[Rob Herring]

On Mon, Jul 9, 2018 at 11:40 AM Sean Paul <seanpaul@chromium.org> wrote:
>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 194 +++++++++++++++++++++++++++
>  1 file changed, 194 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index cdaabeb3c995..339afed856de 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -5,6 +5,8 @@
>   * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>   */
>
> +#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>
>  / {
> @@ -221,6 +223,198 @@
>                         #interrupt-cells = <2>;
>                 };
>
> +               mdss: mdss@ae00000 {
> +                       compatible = "qcom,dpu-mdss";
> +                       reg = <0xae00000 0x1000>;
> +                       reg-names = "mdss_phys";
> +
> +                       power-domains = <&dispcc 0>;
> +
> +                       clocks = <&gcc GCC_DISP_AHB_CLK>,
> +                                <&gcc GCC_DISP_AXI_CLK>,
> +                                <&dispcc DISP_CC_MDSS_MDP_CLK>;
> +                       clock-names = "iface", "bus", "core";
> +                       clock-frequency = <0 0 300000000>;
> +
> +                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <1>;
> +
> +                       /* iommus = <&apps_iommu 0>; */
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +
> +                       mdss_mdp: mdp@ae01000 {
> +                               compatible = "qcom,dpu";

Needs an SoC specific compatible. Did this binding get reviewed?

> +                               reg = <0x0ae01000 0x8f000>,
> +                                     <0x0aeb0000 0x2008>;
> +                               reg-names = "mdp_phys", "vbif_phys";
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_MDP_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +                               clock-names = "iface", "bus", "core", "vsync";
> +                               clock-frequency = <0 0 300000000 19200000>;

That's abusing clock-frequency which is generally 1 value. Use
assigned-clock-rates instead.

> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               dpu_intf1_out: endpoint {
> +                                                       remote-endpoint = <&dsi0_in>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               dpu_intf2_out: endpoint {
> +                                                       remote-endpoint = <&dsi1_in>;
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       dsi0: dsi@ae94000 {
> +                               compatible = "qcom,mdss-dsi-ctrl";

Needs an SoC specific compatible.

> +                               reg = <0xae94000 0x400>;
> +                               reg-names = "dsi_ctrl";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <4 0>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>;
> +                               clock-names = "byte_clk",
> +                                             "byte_intf_clk",
> +                                             "pixel_clk",
> +                                             "core_clk",
> +                                             "iface_clk",
> +                                             "bus_clk";

Should have found this in binding review, but the "_clk" part is redundant.

> +
> +                               phys = <&dsi0_phy>;
> +                               phy-names = "dsi-phy";
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               dsi0_in: endpoint {
> +                                                       remote-endpoint = <&dpu_intf1_out>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               dsi0_out: endpoint {
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       dsi0_phy: dsi-phy@ae94400 {
> +                               compatible = "qcom,dsi-phy-10nm";
> +                               reg = <0xae94400 0x200>,
> +                                     <0xae94a00 0x1e0>,
> +                                     <0xae94600 0x280>;
> +                               reg-names = "dsi_phy",
> +                                           "dsi_pll",
> +                                           "dsi_phy_lane";
> +
> +                               #clock-cells = <1>;
> +                               #phy-cells = <0>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
> +                               clock-names = "iface_clk";
> +                       };
> +
> +                       dsi1: dsi@ae96000 {
> +                               compatible = "qcom,mdss-dsi-ctrl";
> +                               reg = <0xae96000 0x400>;
> +                               reg-names = "dsi_ctrl";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <5 0>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_ESC1_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>;
> +                               clock-names = "byte_clk",
> +                                             "byte_intf_clk",
> +                                             "pixel_clk",
> +                                             "core_clk",
> +                                             "iface_clk",
> +                                             "bus_clk";
> +
> +                               phys = <&dsi1_phy>;
> +                               phy-names = "dsi-phy";
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               dsi1_in: endpoint {
> +                                                       remote-endpoint = <&dpu_intf2_out>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               dsi1_out: endpoint {
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       dsi1_phy: dsi-phy@ae96400 {
> +                               compatible = "qcom,dsi-phy-10nm";
> +                               reg = <0xae96400 0x200>,
> +                                     <0xae96a00 0x10e>,
> +                                     <0xae96600 0x280>;
> +                               reg-names = "dsi_phy",
> +                                           "dsi_pll",
> +                                           "dsi_phy_lane";
> +
> +                               #clock-cells = <1>;
> +                               #phy-cells = <0>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
> +                               clock-names = "iface_clk";
> +                       };
> +               };
> +
> +               dispcc: qcom,dispcc@af00000 {
> +                       compatible = "qcom,sdm845-dispcc";
> +                       reg = <0xaf00000 0x10000>;
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +               };
> +
>                 spmi_bus: spmi@c440000 {
>                         compatible = "qcom,spmi-pmic-arb";
>                         reg = <0xc440000 0x1100>,
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
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Re: [PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file

[Sean Paul]

On Mon, Jul 09, 2018 at 12:07:11PM -0600, Rob Herring wrote:
> On Mon, Jul 9, 2018 at 11:40 AM Sean Paul <seanpaul@chromium.org> wrote:
> >
> > Signed-off-by: Sean Paul <seanpaul@chromium.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sdm845.dtsi | 194 +++++++++++++++++++++++++++
> >  1 file changed, 194 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index cdaabeb3c995..339afed856de 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -5,6 +5,8 @@
> >   * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> >   */
> >
> > +#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> > +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >
> >  / {
> > @@ -221,6 +223,198 @@
> >                         #interrupt-cells = <2>;
> >                 };
> >
> > +               mdss: mdss@ae00000 {
> > +                       compatible = "qcom,dpu-mdss";
> > +                       reg = <0xae00000 0x1000>;
> > +                       reg-names = "mdss_phys";
> > +
> > +                       power-domains = <&dispcc 0>;
> > +
> > +                       clocks = <&gcc GCC_DISP_AHB_CLK>,
> > +                                <&gcc GCC_DISP_AXI_CLK>,
> > +                                <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > +                       clock-names = "iface", "bus", "core";
> > +                       clock-frequency = <0 0 300000000>;
> > +
> > +                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-controller;
> > +                       #interrupt-cells = <1>;
> > +
> > +                       /* iommus = <&apps_iommu 0>; */
> > +
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +                       ranges;
> > +
> > +                       mdss_mdp: mdp@ae01000 {
> > +                               compatible = "qcom,dpu";
> 

Hi Rob,
Thanks for the quick turnaround! In addition to below, I'll also beef up the
commit message, since I forgot to add any description of the change.


> Needs an SoC specific compatible. Did this binding get reviewed?
> 

No, it's part of this set ([PATCH 19/21] dt-bindings: msm/disp: Add bindings for
Snapdragon 845 DPU).

> > +                               reg = <0x0ae01000 0x8f000>,
> > +                                     <0x0aeb0000 0x2008>;
> > +                               reg-names = "mdp_phys", "vbif_phys";
> > +
> > +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_MDP_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > +                               clock-names = "iface", "bus", "core", "vsync";
> > +                               clock-frequency = <0 0 300000000 19200000>;
> 
> That's abusing clock-frequency which is generally 1 value. Use
> assigned-clock-rates instead.
> 

Thanks, will change.

> > +
> > +                               interrupt-parent = <&mdss>;
> > +                               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                               ports {
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       port@0 {
> > +                                               reg = <0>;
> > +                                               dpu_intf1_out: endpoint {
> > +                                                       remote-endpoint = <&dsi0_in>;
> > +                                               };
> > +                                       };
> > +
> > +                                       port@1 {
> > +                                               reg = <1>;
> > +                                               dpu_intf2_out: endpoint {
> > +                                                       remote-endpoint = <&dsi1_in>;
> > +                                               };
> > +                                       };
> > +                               };
> > +                       };
> > +
> > +                       dsi0: dsi@ae94000 {
> > +                               compatible = "qcom,mdss-dsi-ctrl";
> 
> Needs an SoC specific compatible.
> 

Ok, will add.

> > +                               reg = <0xae94000 0x400>;
> > +                               reg-names = "dsi_ctrl";
> > +
> > +                               interrupt-parent = <&mdss>;
> > +                               interrupts = <4 0>;
> > +
> > +                               clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>;
> > +                               clock-names = "byte_clk",
> > +                                             "byte_intf_clk",
> > +                                             "pixel_clk",
> > +                                             "core_clk",
> > +                                             "iface_clk",
> > +                                             "bus_clk";
> 
> Should have found this in binding review, but the "_clk" part is redundant.
> 

This binding is already in mainline (Documentation/devicetree/bindings/display/msm/dsi.txt),
which is why _clk is here, but not above.

Sean
> > +
> > +                               phys = <&dsi0_phy>;
> > +                               phy-names = "dsi-phy";
> > +
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +
> > +                               ports {
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       port@0 {
> > +                                               reg = <0>;
> > +                                               dsi0_in: endpoint {
> > +                                                       remote-endpoint = <&dpu_intf1_out>;
> > +                                               };
> > +                                       };
> > +
> > +                                       port@1 {
> > +                                               reg = <1>;
> > +                                               dsi0_out: endpoint {
> > +                                               };
> > +                                       };
> > +                               };
> > +                       };
> > +
> > +                       dsi0_phy: dsi-phy@ae94400 {
> > +                               compatible = "qcom,dsi-phy-10nm";
> > +                               reg = <0xae94400 0x200>,
> > +                                     <0xae94a00 0x1e0>,
> > +                                     <0xae94600 0x280>;
> > +                               reg-names = "dsi_phy",
> > +                                           "dsi_pll",
> > +                                           "dsi_phy_lane";
> > +
> > +                               #clock-cells = <1>;
> > +                               #phy-cells = <0>;
> > +
> > +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
> > +                               clock-names = "iface_clk";
> > +                       };
> > +
> > +                       dsi1: dsi@ae96000 {
> > +                               compatible = "qcom,mdss-dsi-ctrl";
> > +                               reg = <0xae96000 0x400>;
> > +                               reg-names = "dsi_ctrl";
> > +
> > +                               interrupt-parent = <&mdss>;
> > +                               interrupts = <5 0>;
> > +
> > +                               clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_ESC1_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>;
> > +                               clock-names = "byte_clk",
> > +                                             "byte_intf_clk",
> > +                                             "pixel_clk",
> > +                                             "core_clk",
> > +                                             "iface_clk",
> > +                                             "bus_clk";
> > +
> > +                               phys = <&dsi1_phy>;
> > +                               phy-names = "dsi-phy";
> > +
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +
> > +                               ports {
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       port@0 {
> > +                                               reg = <0>;
> > +                                               dsi1_in: endpoint {
> > +                                                       remote-endpoint = <&dpu_intf2_out>;
> > +                                               };
> > +                                       };
> > +
> > +                                       port@1 {
> > +                                               reg = <1>;
> > +                                               dsi1_out: endpoint {
> > +                                               };
> > +                                       };
> > +                               };
> > +                       };
> > +
> > +                       dsi1_phy: dsi-phy@ae96400 {
> > +                               compatible = "qcom,dsi-phy-10nm";
> > +                               reg = <0xae96400 0x200>,
> > +                                     <0xae96a00 0x10e>,
> > +                                     <0xae96600 0x280>;
> > +                               reg-names = "dsi_phy",
> > +                                           "dsi_pll",
> > +                                           "dsi_phy_lane";
> > +
> > +                               #clock-cells = <1>;
> > +                               #phy-cells = <0>;
> > +
> > +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
> > +                               clock-names = "iface_clk";
> > +                       };
> > +               };
> > +
> > +               dispcc: qcom,dispcc@af00000 {
> > +                       compatible = "qcom,sdm845-dispcc";
> > +                       reg = <0xaf00000 0x10000>;
> > +                       #clock-cells = <1>;
> > +                       #reset-cells = <1>;
> > +                       #power-domain-cells = <1>;
> > +               };
> > +
> >                 spmi_bus: spmi@c440000 {
> >                         compatible = "qcom,spmi-pmic-arb";
> >                         reg = <0xc440000 0x1100>,
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
> >

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file

[Rob Clark]

On Mon, Jul 9, 2018 at 2:35 PM, Sean Paul <seanpaul@chromium.org> wrote:
> On Mon, Jul 09, 2018 at 12:07:11PM -0600, Rob Herring wrote:
>> On Mon, Jul 9, 2018 at 11:40 AM Sean Paul <seanpaul@chromium.org> wrote:
>> >
>> > Signed-off-by: Sean Paul <seanpaul@chromium.org>
>> > ---
>> >  arch/arm64/boot/dts/qcom/sdm845.dtsi | 194 +++++++++++++++++++++++++++
>> >  1 file changed, 194 insertions(+)
>> >
>> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> > index cdaabeb3c995..339afed856de 100644
>> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> > @@ -5,6 +5,8 @@
>> >   * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> >   */
>> >
>> > +#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
>> > +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
>> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
>> >
>> >  / {
>> > @@ -221,6 +223,198 @@
>> >                         #interrupt-cells = <2>;
>> >                 };
>> >
>> > +               mdss: mdss@ae00000 {
>> > +                       compatible = "qcom,dpu-mdss";
>> > +                       reg = <0xae00000 0x1000>;
>> > +                       reg-names = "mdss_phys";
>> > +
>> > +                       power-domains = <&dispcc 0>;
>> > +
>> > +                       clocks = <&gcc GCC_DISP_AHB_CLK>,
>> > +                                <&gcc GCC_DISP_AXI_CLK>,
>> > +                                <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> > +                       clock-names = "iface", "bus", "core";
>> > +                       clock-frequency = <0 0 300000000>;
>> > +
>> > +                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> > +                       interrupt-controller;
>> > +                       #interrupt-cells = <1>;
>> > +
>> > +                       /* iommus = <&apps_iommu 0>; */
>> > +
>> > +                       #address-cells = <1>;
>> > +                       #size-cells = <1>;
>> > +                       ranges;
>> > +
>> > +                       mdss_mdp: mdp@ae01000 {
>> > +                               compatible = "qcom,dpu";
>>
>
> Hi Rob,
> Thanks for the quick turnaround! In addition to below, I'll also beef up the
> commit message, since I forgot to add any description of the change.
>
>
>> Needs an SoC specific compatible. Did this binding get reviewed?
>>
>
> No, it's part of this set ([PATCH 19/21] dt-bindings: msm/disp: Add bindings for
> Snapdragon 845 DPU).

note that for display controller and DSI we've been able to reliably
read the version of the block from hardware.

BR,
-R

>
>> > +                               reg = <0x0ae01000 0x8f000>,
>> > +                                     <0x0aeb0000 0x2008>;
>> > +                               reg-names = "mdp_phys", "vbif_phys";
>> > +
>> > +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> > +                               clock-names = "iface", "bus", "core", "vsync";
>> > +                               clock-frequency = <0 0 300000000 19200000>;
>>
>> That's abusing clock-frequency which is generally 1 value. Use
>> assigned-clock-rates instead.
>>
>
> Thanks, will change.
>
>> > +
>> > +                               interrupt-parent = <&mdss>;
>> > +                               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> > +
>> > +                               ports {
>> > +                                       #address-cells = <1>;
>> > +                                       #size-cells = <0>;
>> > +
>> > +                                       port@0 {
>> > +                                               reg = <0>;
>> > +                                               dpu_intf1_out: endpoint {
>> > +                                                       remote-endpoint = <&dsi0_in>;
>> > +                                               };
>> > +                                       };
>> > +
>> > +                                       port@1 {
>> > +                                               reg = <1>;
>> > +                                               dpu_intf2_out: endpoint {
>> > +                                                       remote-endpoint = <&dsi1_in>;
>> > +                                               };
>> > +                                       };
>> > +                               };
>> > +                       };
>> > +
>> > +                       dsi0: dsi@ae94000 {
>> > +                               compatible = "qcom,mdss-dsi-ctrl";
>>
>> Needs an SoC specific compatible.
>>
>
> Ok, will add.
>
>> > +                               reg = <0xae94000 0x400>;
>> > +                               reg-names = "dsi_ctrl";
>> > +
>> > +                               interrupt-parent = <&mdss>;
>> > +                               interrupts = <4 0>;
>> > +
>> > +                               clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_ESC0_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>;
>> > +                               clock-names = "byte_clk",
>> > +                                             "byte_intf_clk",
>> > +                                             "pixel_clk",
>> > +                                             "core_clk",
>> > +                                             "iface_clk",
>> > +                                             "bus_clk";
>>
>> Should have found this in binding review, but the "_clk" part is redundant.
>>
>
> This binding is already in mainline (Documentation/devicetree/bindings/display/msm/dsi.txt),
> which is why _clk is here, but not above.
>
> Sean
>> > +
>> > +                               phys = <&dsi0_phy>;
>> > +                               phy-names = "dsi-phy";
>> > +
>> > +                               #address-cells = <1>;
>> > +                               #size-cells = <0>;
>> > +
>> > +                               ports {
>> > +                                       #address-cells = <1>;
>> > +                                       #size-cells = <0>;
>> > +
>> > +                                       port@0 {
>> > +                                               reg = <0>;
>> > +                                               dsi0_in: endpoint {
>> > +                                                       remote-endpoint = <&dpu_intf1_out>;
>> > +                                               };
>> > +                                       };
>> > +
>> > +                                       port@1 {
>> > +                                               reg = <1>;
>> > +                                               dsi0_out: endpoint {
>> > +                                               };
>> > +                                       };
>> > +                               };
>> > +                       };
>> > +
>> > +                       dsi0_phy: dsi-phy@ae94400 {
>> > +                               compatible = "qcom,dsi-phy-10nm";
>> > +                               reg = <0xae94400 0x200>,
>> > +                                     <0xae94a00 0x1e0>,
>> > +                                     <0xae94600 0x280>;
>> > +                               reg-names = "dsi_phy",
>> > +                                           "dsi_pll",
>> > +                                           "dsi_phy_lane";
>> > +
>> > +                               #clock-cells = <1>;
>> > +                               #phy-cells = <0>;
>> > +
>> > +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
>> > +                               clock-names = "iface_clk";
>> > +                       };
>> > +
>> > +                       dsi1: dsi@ae96000 {
>> > +                               compatible = "qcom,mdss-dsi-ctrl";
>> > +                               reg = <0xae96000 0x400>;
>> > +                               reg-names = "dsi_ctrl";
>> > +
>> > +                               interrupt-parent = <&mdss>;
>> > +                               interrupts = <5 0>;
>> > +
>> > +                               clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_ESC1_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> > +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>;
>> > +                               clock-names = "byte_clk",
>> > +                                             "byte_intf_clk",
>> > +                                             "pixel_clk",
>> > +                                             "core_clk",
>> > +                                             "iface_clk",
>> > +                                             "bus_clk";
>> > +
>> > +                               phys = <&dsi1_phy>;
>> > +                               phy-names = "dsi-phy";
>> > +
>> > +                               #address-cells = <1>;
>> > +                               #size-cells = <0>;
>> > +
>> > +                               ports {
>> > +                                       #address-cells = <1>;
>> > +                                       #size-cells = <0>;
>> > +
>> > +                                       port@0 {
>> > +                                               reg = <0>;
>> > +                                               dsi1_in: endpoint {
>> > +                                                       remote-endpoint = <&dpu_intf2_out>;
>> > +                                               };
>> > +                                       };
>> > +
>> > +                                       port@1 {
>> > +                                               reg = <1>;
>> > +                                               dsi1_out: endpoint {
>> > +                                               };
>> > +                                       };
>> > +                               };
>> > +                       };
>> > +
>> > +                       dsi1_phy: dsi-phy@ae96400 {
>> > +                               compatible = "qcom,dsi-phy-10nm";
>> > +                               reg = <0xae96400 0x200>,
>> > +                                     <0xae96a00 0x10e>,
>> > +                                     <0xae96600 0x280>;
>> > +                               reg-names = "dsi_phy",
>> > +                                           "dsi_pll",
>> > +                                           "dsi_phy_lane";
>> > +
>> > +                               #clock-cells = <1>;
>> > +                               #phy-cells = <0>;
>> > +
>> > +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
>> > +                               clock-names = "iface_clk";
>> > +                       };
>> > +               };
>> > +
>> > +               dispcc: qcom,dispcc@af00000 {
>> > +                       compatible = "qcom,sdm845-dispcc";
>> > +                       reg = <0xaf00000 0x10000>;
>> > +                       #clock-cells = <1>;
>> > +                       #reset-cells = <1>;
>> > +                       #power-domain-cells = <1>;
>> > +               };
>> > +
>> >                 spmi_bus: spmi@c440000 {
>> >                         compatible = "qcom,spmi-pmic-arb";
>> >                         reg = <0xc440000 0x1100>,
>> > --
>> > Sean Paul, Software Engineer, Google / Chromium OS
>> >
>
> --
> Sean Paul, Software Engineer, Google / Chromium OS
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[PATCH v2 19/21] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU

[Sean Paul]

From: Jeykumar Sankaran <jsanka@codeaurora.org>

Adds bindings for Snapdragon 845 display processing unit

Changes in v2:
 - Use SoC specific compatibles for mdss and dpu
 - Use assigned-clocks to set initial clock frequency

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 .../devicetree/bindings/display/msm/dpu.txt   | 136 ++++++++++++++++++
 1 file changed, 136 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt

diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt
new file mode 100644
index 000000000000..a998028896ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -0,0 +1,136 @@
+Qualcomm Technologies, Inc. DPU KMS
+
+Description:
+
+Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+sub-blocks like DPU display controller, DSI and DP interfaces etc.
+The DPU display controller is found in SDM845 SoC.
+
+MDSS:
+Required properties:
+- compatible: "qcom,sdm845-mdss"
+- reg: physical base address and length of contoller's registers.
+- reg-names: register region names. The following region is required:
+  * "mdss_phys"
+- power-domains: a power domain consumer specifier according to
+  Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: list of phandles for clock device nodes needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+  The following clocks are required:
+  * "iface"
+  * "bus"
+  * "core"
+- interrupts: interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+  source, should be 1.
+- iommus: phandle of iommu device node.
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
+
+Optional properties:
+- assigned-clocks: list of phandles for clock device nodes needing rate
+		   assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+  the assigned-clocks property.
+
+MDP:
+Required properties:
+- compatible: "qcom,sdm845-dpu"
+- reg: physical base address and length of controller's registers.
+- reg-names : register region names. The following region is required:
+  * "mdp_phys"
+  * "vbif_phys"
+- clocks: list of phandles for clock device nodes needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+  The following clocks are required.
+  * "bus"
+  * "iface"
+  * "core"
+  * "vsync"
+- interrupt-parent: phandle to MDSS block.
+- interrupts: interrupt line from DPU to MDSS.
+- ports: contains the list of output ports from DPU device. These ports connect
+  to interfaces that are external to the DPU hardware, such as DSI, DP etc.
+
+  Each output port contains an endpoint that describes how it is connected to an
+  external interface. These are described by the standard properties documented
+  here:
+	Documentation/devicetree/bindings/graph.txt
+	Documentation/devicetree/bindings/media/video-interfaces.txt
+
+	Port 0 -> DPU_INTF1 (DSI1)
+	Port 1 -> DPU_INTF2 (DSI2)
+
+Optional properties:
+- assigned-clocks: list of phandles for clock device nodes needing rate
+		   assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+  the assigned-clocks property.
+
+Example:
+
+	mdss: mdss@ae00000 {
+		compatible = "qcom,sdm845-mdss";
+		reg = <0xae00000 0x1000>;
+		reg-names = "mdss_phys";
+
+		power-domains = <&clock_dispcc 0>;
+
+		clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
+			 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+		clock-names = "iface", "bus", "core";
+
+		assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+		assigned-clock-rates = <300000000>;
+
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		iommus = <&apps_iommu 0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		mdss_mdp: mdp@ae01000 {
+			compatible = "qcom,sdm845-dpu";
+			reg = <0x0ae01000 0x8f000>,
+			      <0x0aeb0000 0x2008>;
+			reg-names = "mdp_phys", "vbif_phys";
+
+			clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+				 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
+				 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+				 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+			clock-names = "iface", "bus", "core", "vsync";
+
+			assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+					  <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+			assigned-clock-rates = <0 0 300000000 19200000>;
+
+			interrupt-parent = <&mdss>;
+			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dpu_intf1_out: endpoint {
+						remote-endpoint = <&dsi0_in>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dpu_intf2_out: endpoint {
+						remote-endpoint = <&dsi1_in>;
+					};
+				};
+			};
+		};
+	};
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[PATCH v2 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file

[Sean Paul]

DPU is short for the Display Processing Unit. It is the display
controller on Qualcomm SDM845 chips.

While the dts is pretty sparse for sdm845 atm, the only piece
we're missing is the iommu. It's commented out for now, and should be
uncommented once support is provided.

Changes in v2:
 - Beefed up commit message
 - Use SoC specific compatibles for mdss and dpu
 - Use assigned-clocks to set initial clock frequency

Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 200 +++++++++++++++++++++++++++
 1 file changed, 200 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index cdaabeb3c995..f1f4cdc9cb63 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5,6 +5,8 @@
  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -221,6 +223,204 @@
 			#interrupt-cells = <2>;
 		};
 
+		mdss: mdss@ae00000 {
+			compatible = "qcom,sdm845-mdss";
+			reg = <0xae00000 0x1000>;
+			reg-names = "mdss_phys";
+
+			power-domains = <&dispcc 0>;
+
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&gcc GCC_DISP_AXI_CLK>,
+				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
+			clock-names = "iface", "bus", "core";
+
+			assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
+			assigned-clock-rates = <300000000>;
+
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			/* iommus = <&apps_iommu 0>; */
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mdss_mdp: mdp@ae01000 {
+				compatible = "qcom,sdm845-dpu";
+				reg = <0x0ae01000 0x8f000>,
+				      <0x0aeb0000 0x2008>;
+				reg-names = "mdp_phys", "vbif_phys";
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>,
+					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "iface", "bus", "core", "vsync";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+						  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <300000000>,
+						       <19200000>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dpu_intf1_out: endpoint {
+							remote-endpoint = <&dsi0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dpu_intf2_out: endpoint {
+							remote-endpoint = <&dsi1_in>;
+						};
+					};
+				};
+			};
+
+			dsi0: dsi@ae94000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0xae94000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4 0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte_clk",
+					      "byte_intf_clk",
+					      "pixel_clk",
+					      "core_clk",
+					      "iface_clk",
+					      "bus_clk";
+
+				phys = <&dsi0_phy>;
+				phy-names = "dsi-phy";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi0_in: endpoint {
+							remote-endpoint = <&dpu_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi0_phy: dsi-phy@ae94400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0xae94400 0x200>,
+				      <0xae94a00 0x1e0>,
+				      <0xae94600 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_pll",
+					    "dsi_phy_lane";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "iface_clk";
+			};
+
+			dsi1: dsi@ae96000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0xae96000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <5 0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte_clk",
+					      "byte_intf_clk",
+					      "pixel_clk",
+					      "core_clk",
+					      "iface_clk",
+					      "bus_clk";
+
+				phys = <&dsi1_phy>;
+				phy-names = "dsi-phy";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi1_in: endpoint {
+							remote-endpoint = <&dpu_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi1_phy: dsi-phy@ae96400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0xae96400 0x200>,
+				      <0xae96a00 0x10e>,
+				      <0xae96600 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_pll",
+					    "dsi_phy_lane";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "iface_clk";
+			};
+		};
+
+		dispcc: qcom,dispcc@af00000 {
+			compatible = "qcom,sdm845-dispcc";
+			reg = <0xaf00000 0x10000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		spmi_bus: spmi@c440000 {
 			compatible = "qcom,spmi-pmic-arb";
 			reg = <0xc440000 0x1100>,
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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Re: [PATCH v2 19/21] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU

[Rob Herring]

On Thu, Jul 12, 2018 at 05:08:37PM -0400, Sean Paul wrote:
> From: Jeykumar Sankaran <jsanka@codeaurora.org>
> 
> Adds bindings for Snapdragon 845 display processing unit
> 
> Changes in v2:
>  - Use SoC specific compatibles for mdss and dpu
>  - Use assigned-clocks to set initial clock frequency
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> ---
>  .../devicetree/bindings/display/msm/dpu.txt   | 136 ++++++++++++++++++
>  1 file changed, 136 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt
> new file mode 100644
> index 000000000000..a998028896ba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
> @@ -0,0 +1,136 @@
> +Qualcomm Technologies, Inc. DPU KMS
> +
> +Description:
> +
> +Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
> +sub-blocks like DPU display controller, DSI and DP interfaces etc.
> +The DPU display controller is found in SDM845 SoC.
> +
> +MDSS:
> +Required properties:
> +- compatible: "qcom,sdm845-mdss"
> +- reg: physical base address and length of contoller's registers.
> +- reg-names: register region names. The following region is required:
> +  * "mdss_phys"

phys as in physical address? If so, that's always the case. *-names is 
pointless when there is only one anyways.

> +- power-domains: a power domain consumer specifier according to
> +  Documentation/devicetree/bindings/power/power_domain.txt
> +- clocks: list of phandles for clock device nodes needed by the device.
> +- clock-names: device clock names, must be in same order as clocks property.
> +  The following clocks are required:
> +  * "iface"
> +  * "bus"
> +  * "core"
> +- interrupts: interrupt signal from MDSS.
> +- interrupt-controller: identifies the node as an interrupt controller.
> +- #interrupt-cells: specifies the number of cells needed to encode an interrupt
> +  source, should be 1.
> +- iommus: phandle of iommu device node.
> +- #address-cells: number of address cells for the MDSS children. Should be 1.
> +- #size-cells: Should be 1.
> +- ranges: parent bus address space is the same as the child bus address space.
> +
> +Optional properties:
> +- assigned-clocks: list of phandles for clock device nodes needing rate

It's a list of clock specifiers (phandle and id), not device nodes.

> +		   assignment
> +- assigned-clock-rates: list of clock frequencies sorted in the same order as
> +  the assigned-clocks property.
> +
> +MDP:
> +Required properties:
> +- compatible: "qcom,sdm845-dpu"
> +- reg: physical base address and length of controller's registers.
> +- reg-names : register region names. The following region is required:
> +  * "mdp_phys"
> +  * "vbif_phys"

Same comment on "_phys" here.

> +- clocks: list of phandles for clock device nodes needed by the device.
> +- clock-names: device clock names, must be in same order as clocks property.
> +  The following clocks are required.
> +  * "bus"
> +  * "iface"
> +  * "core"
> +  * "vsync"
> +- interrupt-parent: phandle to MDSS block.

Actually, you don't need this if a parent node contains 
"interrupt-controller" property.

> +- interrupts: interrupt line from DPU to MDSS.
> +- ports: contains the list of output ports from DPU device. These ports connect
> +  to interfaces that are external to the DPU hardware, such as DSI, DP etc.
> +
> +  Each output port contains an endpoint that describes how it is connected to an
> +  external interface. These are described by the standard properties documented
> +  here:
> +	Documentation/devicetree/bindings/graph.txt
> +	Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> +	Port 0 -> DPU_INTF1 (DSI1)
> +	Port 1 -> DPU_INTF2 (DSI2)
> +
> +Optional properties:
> +- assigned-clocks: list of phandles for clock device nodes needing rate
> +		   assignment
> +- assigned-clock-rates: list of clock frequencies sorted in the same order as
> +  the assigned-clocks property.
> +
> +Example:
> +
> +	mdss: mdss@ae00000 {
> +		compatible = "qcom,sdm845-mdss";
> +		reg = <0xae00000 0x1000>;
> +		reg-names = "mdss_phys";
> +
> +		power-domains = <&clock_dispcc 0>;
> +
> +		clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
> +			 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
> +		clock-names = "iface", "bus", "core";
> +
> +		assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
> +		assigned-clock-rates = <300000000>;
> +
> +		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +
> +		iommus = <&apps_iommu 0>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;

It's preferred to put actual values in and limit the range of child 
nodes. Is there anything in 0xae90000-0xaeaffff?

> +
> +		mdss_mdp: mdp@ae01000 {
> +			compatible = "qcom,sdm845-dpu";
> +			reg = <0x0ae01000 0x8f000>,
> +			      <0x0aeb0000 0x2008>;
> +			reg-names = "mdp_phys", "vbif_phys";
> +
> +			clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
> +				 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
> +				 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
> +				 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +			clock-names = "iface", "bus", "core", "vsync";
> +
> +			assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
> +					  <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +			assigned-clock-rates = <0 0 300000000 19200000>;
> +
> +			interrupt-parent = <&mdss>;
> +			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					dpu_intf1_out: endpoint {
> +						remote-endpoint = <&dsi0_in>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +					dpu_intf2_out: endpoint {
> +						remote-endpoint = <&dsi1_in>;
> +					};
> +				};
> +			};
> +		};
> +	};
> -- 
> Sean Paul, Software Engineer, Google / Chromium OS
> 
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Re: [PATCH 01/21] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding

[Rob Herring]

On Mon, Jul 09, 2018 at 01:31:37PM -0400, Sean Paul wrote:
> From: Jeykumar Sankaran <jsanka@codeaurora.org>
> 
> Adds mdp transfer time to msm dsi binding
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> ---
>  .../devicetree/bindings/display/msm/dsi.txt      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Reviewed-by: Rob Herring <robh@kernel.org>
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