From: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
To: Rob Herring <robh@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>, Andrew Lunn <andrew@lunn.ch>,
Jason Cooper <jason@lakedaemon.net>,
devicetree@vger.kernel.org, Marc Zyngier <marc.zyngier@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Gregory Clement <gregory.clement@bootlin.com>,
Haim Boot <hayim@marvell.com>, Will Deacon <will.deacon@arm.com>,
Maxime Chevallier <maxime.chevallier@bootlin.com>,
Nadav Haklai <nadavh@marvell.com>,
Antoine Tenart <antoine.tenart@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Thomas Gleixner <tglx@linutronix.de>,
Hanna Hawa <hannah@marvell.com>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v4 10/14] dt-bindings/interrupt-controller: update Marvell ICU bindings
Date: Mon, 16 Jul 2018 21:38:19 +0200 [thread overview]
Message-ID: <20180716213819.48e13e4d@windsurf> (raw)
In-Reply-To: <20180716152734.GA4581@rob-hp-laptop>
Hello,
On Mon, 16 Jul 2018 09:27:34 -0600, Rob Herring wrote:
> > +Required properties for the icu_nsr/icu_sei subnodes:
> > +
> > +- compatible: Should be "marvell,cp110-icu-nsr" or "marvell,cp110-icu-sei".
> > +
>
> I raised this before and still don't understand. You had 4 types before
> and now you only have 2 types? How do you handle SR and REI with the new
> binding?
As I replied to a different e-mail, the current binding pretended to
support SR, SEI and REI, but it definitely could not.
The ICU collects wired interrupts from the CP, and forwards them to the
AP as MSIs. And contrary to what we thought when designing the current
binding, the target of the MSIs is different depending on the type of
interrupt. NSRs go to the GICP controller in the AP, SEIs go to a
special SEI controller in the AP, REIs go to a special REI controller
in the AP.
In order to represent that in the Device Tree, you need to have a
different msi-parent property for each of NSR, SEI and REI. This is not
something that the current broken binding allows to express, and it's
the reason why we're migrating to this new binding.
So even if the current binding documents that it supports NSR, SEI, REI
and SR, it definitely cannot support anything but NSR. Therefore, the
introduction of the new binding by Miquèl does not introduce any
regression in functionality: it simply allows to really support SEIs.
Does this explanation clarify the situation, and what we're trying to
achieve ?
Thanks!
Thomas
--
Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2018-07-16 19:38 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-05 12:39 [PATCH v4 00/14] Add System Error Interrupt support to Armada SoCs Miquel Raynal
2018-07-05 12:39 ` [PATCH v4 01/14] genirq/msi: Allow creation of a tree-based irqdomain for platform-msi Miquel Raynal
2018-07-05 12:39 ` [PATCH v4 02/14] dt-bindings/interrupt-controller: fix Marvell ICU length in the example Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 03/14] irqchip/irq-mvebu-icu: fix wrong private data retrieval Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 04/14] irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 05/14] irqchip/irq-mvebu-icu: disociate ICU and NSR Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 06/14] irqchip/irq-mvebu-icu: support ICU subnodes Miquel Raynal
2018-08-20 14:16 ` Marc Zyngier
2018-07-05 12:40 ` [PATCH v4 07/14] irqchip/irq-mvebu-sei: add new driver for Marvell SEI Miquel Raynal
2018-08-20 14:58 ` Marc Zyngier
2018-07-05 12:40 ` [PATCH v4 08/14] arm64: marvell: enable SEI driver Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 09/14] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) Miquel Raynal
2018-08-20 15:21 ` Marc Zyngier
2018-08-21 9:08 ` Miquel Raynal
2018-08-21 9:19 ` Marc Zyngier
2018-08-21 10:28 ` Miquel Raynal
2018-08-21 10:37 ` Marc Zyngier
2018-08-21 15:41 ` Miquel Raynal
2018-08-23 11:44 ` Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 10/14] dt-bindings/interrupt-controller: update Marvell ICU bindings Miquel Raynal
2018-07-16 15:27 ` Rob Herring
2018-07-16 16:39 ` Miquel Raynal
2018-07-16 17:44 ` Rob Herring
2018-07-16 19:30 ` Thomas Petazzoni
2018-07-16 19:38 ` Thomas Petazzoni [this message]
2018-07-05 12:40 ` [PATCH v4 11/14] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 12/14] arm64: dts: marvell: add AP806 SEI subnode Miquel Raynal
2018-07-16 15:31 ` Rob Herring
2018-07-05 12:40 ` [PATCH v4 13/14] arm64: dts: marvell: use new bindings for CP110 interrupts Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 14/14] arm64: dts: marvell: add CP110 ICU SEI subnode Miquel Raynal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180716213819.48e13e4d@windsurf \
--to=thomas.petazzoni@bootlin.com \
--cc=andrew@lunn.ch \
--cc=antoine.tenart@bootlin.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=gregory.clement@bootlin.com \
--cc=hannah@marvell.com \
--cc=hayim@marvell.com \
--cc=jason@lakedaemon.net \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=maxime.chevallier@bootlin.com \
--cc=miquel.raynal@bootlin.com \
--cc=nadavh@marvell.com \
--cc=robh@kernel.org \
--cc=sebastian.hesselbarth@gmail.com \
--cc=tglx@linutronix.de \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).