* [PATCH V2 09/25] dt-bindings: PCI: qcom,ar7100: adds binding doc [not found] <20180720115842.8406-1-john@phrozen.org> @ 2018-07-20 11:58 ` John Crispin 2018-07-20 15:51 ` Sergei Shtylyov 2018-07-20 15:58 ` Sergei Shtylyov 2018-07-20 11:58 ` [PATCH V2 11/25] dt-bindings: PCI: qcom,ar7240: " John Crispin 1 sibling, 2 replies; 6+ messages in thread From: John Crispin @ 2018-07-20 11:58 UTC (permalink / raw) To: James Hogan, Ralf Baechle Cc: linux-mips, John Crispin, Rob Herring, devicetree With the driver being converted from platform_data to pure OF, we need to also add some docs. Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: John Crispin <john@phrozen.org> --- .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt new file mode 100644 index 000000000000..10085dd1cd11 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt @@ -0,0 +1,38 @@ +* Qualcomm Atheros AR7100 PCI express root complex + +Required properties: +- compatible: should contain "qcom,ar7100-pci" to identify the core. +- reg: Should contain the register ranges as listed in the reg-names property. +- reg-names: Definition: Must include the following entries + - "cfg_base" IO Memory +- #address-cells: set to <3> +- #size-cells: set to <2> +- ranges: ranges for the PCI memory and I/O regions +- interrupt-map-mask and interrupt-map: standard PCI + properties to define the mapping of the PCIe interface to interrupt + numbers. +- #interrupt-cells: set to <1> +- interrupt-controller: define to enable the builtin IRQ cascade. + +Optional properties: +- interrupt-parent: phandle to the MIPS IRQ controller + +* Example for ar7100 + pcie-controller@180c0000 { + compatible = "qca,ar7100-pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x0>; + reg = <0x17010000 0x100>; + reg-names = "cfg_base"; + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 1>; + interrupt-map = <0 0 0 0 &pcie0 0>; + }; -- 2.11.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V2 09/25] dt-bindings: PCI: qcom,ar7100: adds binding doc 2018-07-20 11:58 ` [PATCH V2 09/25] dt-bindings: PCI: qcom,ar7100: adds binding doc John Crispin @ 2018-07-20 15:51 ` Sergei Shtylyov 2018-07-20 15:58 ` Sergei Shtylyov 1 sibling, 0 replies; 6+ messages in thread From: Sergei Shtylyov @ 2018-07-20 15:51 UTC (permalink / raw) To: John Crispin, James Hogan, Ralf Baechle Cc: linux-mips, Rob Herring, devicetree On 07/20/2018 02:58 PM, John Crispin wrote: > With the driver being converted from platform_data to pure OF, we need to > also add some docs. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: John Crispin <john@phrozen.org> > --- > .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt > > diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt > new file mode 100644 > index 000000000000..10085dd1cd11 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt > @@ -0,0 +1,38 @@ > +* Qualcomm Atheros AR7100 PCI express root complex > + > +Required properties: > +- compatible: should contain "qcom,ar7100-pci" to identify the core. > +- reg: Should contain the register ranges as listed in the reg-names property. > +- reg-names: Definition: Must include the following entries > + - "cfg_base" IO Memory > +- #address-cells: set to <3> > +- #size-cells: set to <2> > +- ranges: ranges for the PCI memory and I/O regions > +- interrupt-map-mask and interrupt-map: standard PCI > + properties to define the mapping of the PCIe interface to interrupt > + numbers. > +- #interrupt-cells: set to <1> > +- interrupt-controller: define to enable the builtin IRQ cascade. > + > +Optional properties: > +- interrupt-parent: phandle to the MIPS IRQ controller > + > +* Example for ar7100 > + pcie-controller@180c0000 { > + compatible = "qca,ar7100-pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x0 0x0>; Not documented above. > + reg = <0x17010000 0x100>; > + reg-names = "cfg_base"; > + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 > + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; > + interrupt-parent = <&cpuintc>; > + interrupts = <2>; Not documented above. [...] MBR, Sergei ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2 09/25] dt-bindings: PCI: qcom,ar7100: adds binding doc 2018-07-20 11:58 ` [PATCH V2 09/25] dt-bindings: PCI: qcom,ar7100: adds binding doc John Crispin 2018-07-20 15:51 ` Sergei Shtylyov @ 2018-07-20 15:58 ` Sergei Shtylyov 1 sibling, 0 replies; 6+ messages in thread From: Sergei Shtylyov @ 2018-07-20 15:58 UTC (permalink / raw) To: John Crispin, James Hogan, Ralf Baechle Cc: linux-mips, Rob Herring, devicetree On 07/20/2018 02:58 PM, John Crispin wrote: > With the driver being converted from platform_data to pure OF, we need to > also add some docs. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: John Crispin <john@phrozen.org> > --- > .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt > > diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt > new file mode 100644 > index 000000000000..10085dd1cd11 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt > @@ -0,0 +1,38 @@ > +* Qualcomm Atheros AR7100 PCI express root complex > + > +Required properties: > +- compatible: should contain "qcom,ar7100-pci" to identify the core. > +- reg: Should contain the register ranges as listed in the reg-names property. > +- reg-names: Definition: Must include the following entries > + - "cfg_base" IO Memory > +- #address-cells: set to <3> > +- #size-cells: set to <2> > +- ranges: ranges for the PCI memory and I/O regions > +- interrupt-map-mask and interrupt-map: standard PCI > + properties to define the mapping of the PCIe interface to interrupt > + numbers. > +- #interrupt-cells: set to <1> > +- interrupt-controller: define to enable the builtin IRQ cascade. > + > +Optional properties: > +- interrupt-parent: phandle to the MIPS IRQ controller > + > +* Example for ar7100 > + pcie-controller@180c0000 { Overlooked it -- should be just "pcie@180c0000". > + compatible = "qca,ar7100-pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x0 0x0>; > + reg = <0x17010000 0x100>; Doesn't match the <unit-address> part of the node name above. > + reg-names = "cfg_base"; > + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 > + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; 1 byte?! [...] MNR, Sergei ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V2 11/25] dt-bindings: PCI: qcom,ar7240: adds binding doc [not found] <20180720115842.8406-1-john@phrozen.org> 2018-07-20 11:58 ` [PATCH V2 09/25] dt-bindings: PCI: qcom,ar7100: adds binding doc John Crispin @ 2018-07-20 11:58 ` John Crispin 2018-07-20 16:11 ` Sergei Shtylyov 2018-07-25 17:34 ` Rob Herring 1 sibling, 2 replies; 6+ messages in thread From: John Crispin @ 2018-07-20 11:58 UTC (permalink / raw) To: James Hogan, Ralf Baechle Cc: linux-mips, John Crispin, Rob Herring, devicetree With the driver being converted from platform_data to pure OF, we need to also add some docs. Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: John Crispin <john@phrozen.org> --- .../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt new file mode 100644 index 000000000000..5379affd4615 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt @@ -0,0 +1,42 @@ +* Qualcomm Atheros AR724X PCI express root complex + +Required properties: +- compatible: should contain "qcom,ar7240-pci" to identify the core. +- reg: Should contain the register ranges as listed in the reg-names property. +- reg-names: Definition: Must include the following entries + - "crp_base" Configuration registers + - "ctrl_base" Control registers + - "cfg_base" IO Memory +- #address-cells: set to <3> +- #size-cells: set to <2> +- ranges: ranges for the PCI memory and I/O regions +- interrupt-map-mask and interrupt-map: standard PCI + properties to define the mapping of the PCIe interface to interrupt + numbers. +- #interrupt-cells: set to <1> +- interrupt-parent: phandle to the MIPS IRQ controller + +Optional properties: +- interrupt-controller: define to enable the builtin IRQ cascade. + +* Example for qca9557 + pcie-controller@180c0000 { + compatible = "qcom,ar7240-pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x0>; + reg = <0x180c0000 0x1000>, + <0x180f0000 0x100>, + <0x14000000 0x1000>; + reg-names = "crp_base", "ctrl_base", "cfg_base"; + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; + interrupt-parent = <&intc2>; + interrupts = <1>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 1>; + interrupt-map = <0 0 0 0 &pcie0 0>; + }; -- 2.11.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V2 11/25] dt-bindings: PCI: qcom,ar7240: adds binding doc 2018-07-20 11:58 ` [PATCH V2 11/25] dt-bindings: PCI: qcom,ar7240: " John Crispin @ 2018-07-20 16:11 ` Sergei Shtylyov 2018-07-25 17:34 ` Rob Herring 1 sibling, 0 replies; 6+ messages in thread From: Sergei Shtylyov @ 2018-07-20 16:11 UTC (permalink / raw) To: John Crispin, James Hogan, Ralf Baechle Cc: linux-mips, Rob Herring, devicetree On 07/20/2018 02:58 PM, John Crispin wrote: > With the driver being converted from platform_data to pure OF, we need to > also add some docs. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: John Crispin <john@phrozen.org> > --- > .../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt > > diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt > new file mode 100644 > index 000000000000..5379affd4615 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt > @@ -0,0 +1,42 @@ > +* Qualcomm Atheros AR724X PCI express root complex > + > +Required properties: > +- compatible: should contain "qcom,ar7240-pci" to identify the core. > +- reg: Should contain the register ranges as listed in the reg-names property. > +- reg-names: Definition: Must include the following entries > + - "crp_base" Configuration registers > + - "ctrl_base" Control registers > + - "cfg_base" IO Memory > +- #address-cells: set to <3> > +- #size-cells: set to <2> > +- ranges: ranges for the PCI memory and I/O regions > +- interrupt-map-mask and interrupt-map: standard PCI > + properties to define the mapping of the PCIe interface to interrupt > + numbers. > +- #interrupt-cells: set to <1> > +- interrupt-parent: phandle to the MIPS IRQ controller > + > +Optional properties: > +- interrupt-controller: define to enable the builtin IRQ cascade. > + > +* Example for qca9557 > + pcie-controller@180c0000 { Just "pcie@180c0000". > + compatible = "qcom,ar7240-pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x0 0x0>; Not described above. > + reg = <0x180c0000 0x1000>, > + <0x180f0000 0x100>, > + <0x14000000 0x1000>; > + reg-names = "crp_base", "ctrl_base", "cfg_base"; > + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 > + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; > + interrupt-parent = <&intc2>; > + interrupts = <1>; Not described also. [...] MBR, Sergei ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2 11/25] dt-bindings: PCI: qcom,ar7240: adds binding doc 2018-07-20 11:58 ` [PATCH V2 11/25] dt-bindings: PCI: qcom,ar7240: " John Crispin 2018-07-20 16:11 ` Sergei Shtylyov @ 2018-07-25 17:34 ` Rob Herring 1 sibling, 0 replies; 6+ messages in thread From: Rob Herring @ 2018-07-25 17:34 UTC (permalink / raw) To: John Crispin; +Cc: James Hogan, Ralf Baechle, linux-mips, devicetree On Fri, Jul 20, 2018 at 01:58:28PM +0200, John Crispin wrote: > With the driver being converted from platform_data to pure OF, we need to > also add some docs. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: John Crispin <john@phrozen.org> > --- > .../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt > > diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt > new file mode 100644 > index 000000000000..5379affd4615 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt > @@ -0,0 +1,42 @@ > +* Qualcomm Atheros AR724X PCI express root complex > + > +Required properties: > +- compatible: should contain "qcom,ar7240-pci" to identify the core. > +- reg: Should contain the register ranges as listed in the reg-names property. > +- reg-names: Definition: Must include the following entries > + - "crp_base" Configuration registers > + - "ctrl_base" Control registers > + - "cfg_base" IO Memory '_base' is redundant. Same question as v1 remains: IO or config space? IO space goes in ranges and config space goes in reg. > +- #address-cells: set to <3> > +- #size-cells: set to <2> > +- ranges: ranges for the PCI memory and I/O regions > +- interrupt-map-mask and interrupt-map: standard PCI > + properties to define the mapping of the PCIe interface to interrupt > + numbers. > +- #interrupt-cells: set to <1> > +- interrupt-parent: phandle to the MIPS IRQ controller This property is implied (and could be in a parent node). Sergei pointed this out in v1 for the 7100. > + > +Optional properties: > +- interrupt-controller: define to enable the builtin IRQ cascade. > + > +* Example for qca9557 > + pcie-controller@180c0000 { pcie@... Also pointed out in v1... > + compatible = "qcom,ar7240-pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x0 0x0>; > + reg = <0x180c0000 0x1000>, > + <0x180f0000 0x100>, > + <0x14000000 0x1000>; > + reg-names = "crp_base", "ctrl_base", "cfg_base"; > + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 > + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; > + interrupt-parent = <&intc2>; > + interrupts = <1>; > + > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interrupt-map-mask = <0 0 0 1>; > + interrupt-map = <0 0 0 0 &pcie0 0>; > + }; > -- > 2.11.0 > ^ permalink raw reply [flat|nested] 6+ messages in thread
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2018-07-20 11:58 ` [PATCH V2 09/25] dt-bindings: PCI: qcom,ar7100: adds binding doc John Crispin
2018-07-20 15:51 ` Sergei Shtylyov
2018-07-20 15:58 ` Sergei Shtylyov
2018-07-20 11:58 ` [PATCH V2 11/25] dt-bindings: PCI: qcom,ar7240: " John Crispin
2018-07-20 16:11 ` Sergei Shtylyov
2018-07-25 17:34 ` Rob Herring
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