* [PATCH] MIPS: mscc: ocelot: add MIIM1 bus
@ 2018-07-25 12:22 Quentin Schulz
2018-07-25 12:31 ` Alexandre Belloni
2018-07-26 17:41 ` Paul Burton
0 siblings, 2 replies; 3+ messages in thread
From: Quentin Schulz @ 2018-07-25 12:22 UTC (permalink / raw)
To: alexandre.belloni, robh+dt, mark.rutland
Cc: ralf, paul.burton, jhogan, linux-mips, devicetree, linux-kernel,
thomas.petazzoni, Quentin Schulz
There is an additional MIIM (MDIO) bus in this SoC so let's declare it
in the dtsi.
This bus requires GPIO 14 and 15 pins that need to be muxed. There is no
support for internal PHY reset on this bus on the contrary of MIIM0 so
there is only one register address space and not two.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
---
arch/mips/boot/dts/mscc/ocelot.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index 7096915f26e0..d7f0e3551500 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -178,6 +178,11 @@
pins = "GPIO_12", "GPIO_13";
function = "uart2";
};
+
+ miim1: miim1 {
+ pins = "GPIO_14", "GPIO_15";
+ function = "miim1";
+ };
};
mdio0: mdio@107009c {
@@ -201,5 +206,16 @@
reg = <3>;
};
};
+
+ mdio1: mdio@10700c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,ocelot-miim";
+ reg = <0x10700c0 0x24>;
+ interrupts = <15>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&miim1>;
+ status = "disabled";
+ };
};
};
--
2.14.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] MIPS: mscc: ocelot: add MIIM1 bus
2018-07-25 12:22 [PATCH] MIPS: mscc: ocelot: add MIIM1 bus Quentin Schulz
@ 2018-07-25 12:31 ` Alexandre Belloni
2018-07-26 17:41 ` Paul Burton
1 sibling, 0 replies; 3+ messages in thread
From: Alexandre Belloni @ 2018-07-25 12:31 UTC (permalink / raw)
To: Quentin Schulz
Cc: robh+dt, mark.rutland, ralf, paul.burton, jhogan, linux-mips,
devicetree, linux-kernel, thomas.petazzoni
On 25/07/2018 14:22:41+0200, Quentin Schulz wrote:
> There is an additional MIIM (MDIO) bus in this SoC so let's declare it
> in the dtsi.
>
> This bus requires GPIO 14 and 15 pins that need to be muxed. There is no
> support for internal PHY reset on this bus on the contrary of MIIM0 so
> there is only one register address space and not two.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> arch/mips/boot/dts/mscc/ocelot.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> index 7096915f26e0..d7f0e3551500 100644
> --- a/arch/mips/boot/dts/mscc/ocelot.dtsi
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -178,6 +178,11 @@
> pins = "GPIO_12", "GPIO_13";
> function = "uart2";
> };
> +
> + miim1: miim1 {
> + pins = "GPIO_14", "GPIO_15";
> + function = "miim1";
> + };
> };
>
> mdio0: mdio@107009c {
> @@ -201,5 +206,16 @@
> reg = <3>;
> };
> };
> +
> + mdio1: mdio@10700c0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "mscc,ocelot-miim";
> + reg = <0x10700c0 0x24>;
> + interrupts = <15>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&miim1>;
> + status = "disabled";
> + };
> };
> };
> --
> 2.14.1
>
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] MIPS: mscc: ocelot: add MIIM1 bus
2018-07-25 12:22 [PATCH] MIPS: mscc: ocelot: add MIIM1 bus Quentin Schulz
2018-07-25 12:31 ` Alexandre Belloni
@ 2018-07-26 17:41 ` Paul Burton
1 sibling, 0 replies; 3+ messages in thread
From: Paul Burton @ 2018-07-26 17:41 UTC (permalink / raw)
To: Quentin Schulz
Cc: alexandre.belloni, robh+dt, mark.rutland, ralf, jhogan,
linux-mips, devicetree, linux-kernel, thomas.petazzoni
Hi Quentin,
On Wed, Jul 25, 2018 at 02:22:41PM +0200, Quentin Schulz wrote:
> There is an additional MIIM (MDIO) bus in this SoC so let's declare it
> in the dtsi.
>
> This bus requires GPIO 14 and 15 pins that need to be muxed. There is no
> support for internal PHY reset on this bus on the contrary of MIIM0 so
> there is only one register address space and not two.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
> ---
> arch/mips/boot/dts/mscc/ocelot.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
Thanks - applied to mips-next for 4.19.
Paul
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-07-26 17:41 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-07-25 12:22 [PATCH] MIPS: mscc: ocelot: add MIIM1 bus Quentin Schulz
2018-07-25 12:31 ` Alexandre Belloni
2018-07-26 17:41 ` Paul Burton
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).