From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH] ARM: dts: sun8i: Add initial Orangepi Zero Plus 2 H3 support Date: Mon, 30 Jul 2018 10:45:19 +0200 Message-ID: <20180730084519.iqyhvocxsfuopze7@flea> References: <20180727125739.22871-1-diego.rondini@kynetics.com> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="5k6awrech3twpden" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20180727125739.22871-1-diego.rondini-WVsNeAwskfdWk0Htik3J/w@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Diego Rondini Cc: Rob Herring , Mark Rutland , Chen-Yu Tsai , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Jagan Teki List-Id: devicetree@vger.kernel.org --5k6awrech3twpden Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Fri, Jul 27, 2018 at 02:57:39PM +0200, Diego Rondini wrote: > +/dts-v1/; > + > +#include "sun8i-h3.dtsi" > + > +#include > + > +/ { > + model = "OrangePi Zero Plus2 H3"; > + compatible = "xunlong,orangepi-zero-plus2", "allwinner,sun8i-h3"; The H5 version doesn't make that easy, and it's unfortunate, but we should have a different compatible for the H3 and H5 versions. What about something like xunlong,orangepi-zero-plus2-h3? > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; > + status = "okay"; > +}; I guess it is the BT chip? Which chip is it? Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com --5k6awrech3twpden--