From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexandre Belloni Subject: Re: [PATCH net-next 02/10] dt-bindings: net: ocelot: remove hsio from the list of register address spaces Date: Tue, 31 Jul 2018 09:52:43 +0200 Message-ID: <20180731075243.GO28585@piout.net> References: <3558e538b55a2249b0a179c04c27e9d3715bbbaa.1532954208.git-series.quentin.schulz@bootlin.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <3558e538b55a2249b0a179c04c27e9d3715bbbaa.1532954208.git-series.quentin.schulz@bootlin.com> Sender: linux-kernel-owner@vger.kernel.org To: Quentin Schulz Cc: ralf@linux-mips.org, paul.burton@mips.com, jhogan@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, davem@davemloft.net, kishon@ti.com, andrew@lunn.ch, f.fainelli@gmail.com, linux-mips@linux-mips.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, allan.nielsen@microsemi.com, thomas.petazzoni@bootlin.com List-Id: devicetree@vger.kernel.org On 30/07/2018 14:43:47+0200, Quentin Schulz wrote: > HSIO register address space should be handled outside of the MAC > controller as there are some registers for PLL5 configuring, > SerDes/switch port muxing and a thermal sensor IP, so let's remove it. > > Signed-off-by: Quentin Schulz Acked-by: Alexandre Belloni > --- > Documentation/devicetree/bindings/mips/mscc.txt | 16 ++++++++++++- > Documentation/devicetree/bindings/net/mscc-ocelot.txt | 9 ++----- > 2 files changed, 19 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt > index ae15ec3..bc817e9 100644 > --- a/Documentation/devicetree/bindings/mips/mscc.txt > +++ b/Documentation/devicetree/bindings/mips/mscc.txt > @@ -41,3 +41,19 @@ Example: > compatible = "mscc,ocelot-cpu-syscon", "syscon"; > reg = <0x70000000 0x2c>; > }; > + > +o HSIO regs: > + > +The SoC has a few registers (HSIO) handling miscellaneous functionalities: > +configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and > +status, SerDes muxing and a thermal sensor. > + > +Required properties: > +- compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd" > +- reg : Should contain registers location and length > + > +Example: > + syscon@10d0000 { > + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; > + reg = <0x10d0000 0x10000>; > + }; > diff --git a/Documentation/devicetree/bindings/net/mscc-ocelot.txt b/Documentation/devicetree/bindings/net/mscc-ocelot.txt > index 0a84711..9e5c17d 100644 > --- a/Documentation/devicetree/bindings/net/mscc-ocelot.txt > +++ b/Documentation/devicetree/bindings/net/mscc-ocelot.txt > @@ -12,7 +12,6 @@ Required properties: > - "sys" > - "rew" > - "qs" > - - "hsio" > - "qsys" > - "ana" > - "portX" with X from 0 to the number of last port index available on that > @@ -45,7 +44,6 @@ Example: > reg = <0x1010000 0x10000>, > <0x1030000 0x10000>, > <0x1080000 0x100>, > - <0x10d0000 0x10000>, > <0x11e0000 0x100>, > <0x11f0000 0x100>, > <0x1200000 0x100>, > @@ -59,10 +57,9 @@ Example: > <0x1280000 0x100>, > <0x1800000 0x80000>, > <0x1880000 0x10000>; > - reg-names = "sys", "rew", "qs", "hsio", "port0", > - "port1", "port2", "port3", "port4", "port5", > - "port6", "port7", "port8", "port9", "port10", > - "qsys", "ana"; > + reg-names = "sys", "rew", "qs", "port0", "port1", "port2", > + "port3", "port4", "port5", "port6", "port7", > + "port8", "port9", "port10", "qsys", "ana"; > interrupts = <21 22>; > interrupt-names = "xtr", "inj"; > > -- > git-series 0.9.1 -- Alexandre Belloni, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com