From: Christoph Hellwig <hch@lst.de>
To: Rob Herring <robh+dt@kernel.org>
Cc: atish.patra@wdc.com, Christoph Hellwig <hch@lst.de>,
Thomas Gleixner <tglx@linutronix.de>,
Palmer Dabbelt <palmer@sifive.com>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
linux-riscv@lists.infradead.org,
Stafford Horne <shorne@gmail.com>
Subject: Re: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation
Date: Tue, 7 Aug 2018 09:20:34 +0200 [thread overview]
Message-ID: <20180807072034.GA569@lst.de> (raw)
In-Reply-To: <CAL_Jsq+pVzqKUbhErRr15JX2mPUOSTp_ddGvu9KAuf=TtXfduQ@mail.gmail.com>
On Mon, Aug 06, 2018 at 02:59:48PM -0600, Rob Herring wrote:
> > > +Required properties:
> > > +- compatible : "sifive,plic0"
> > > +- #address-cells : should be <0>
> > > +- #interrupt-cells : should be <1>
> > > +- interrupt-controller : Identifies the node as an interrupt controller
> > > +- reg : Should contain 1 register range (address and length)
> >
> > The one in the real device tree has two entries.
> > reg = <0x00000000 0x0c000000 0x00000000 0x04000000>;
> >
> > Is it intentional or just incorrect entry left over from earlier days?
>
> > > + reg = <0xc000000 0x4000000>;
>
> Looks to me like one has #size-cells and #address-cells set to 2 and
> the example is using 1.
Yes. And it seems like the real life device tree is simply bogus.
next prev parent reply other threads:[~2018-08-07 7:20 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-02 11:49 simplified RISC-V interrupt and clocksource handling v2 Christoph Hellwig
2018-08-02 11:49 ` [PATCH 01/11] dt-bindings: Correct RISC-V's timebase-frequency Christoph Hellwig
2018-08-08 14:44 ` Rob Herring
2018-08-02 11:49 ` [PATCH 02/11] dt-bindings: Add an enable method to RISC-V Christoph Hellwig
2018-08-08 14:43 ` Rob Herring
2018-08-02 11:50 ` [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-02 22:08 ` Atish Patra
2018-08-03 13:30 ` Christoph Hellwig
2018-08-06 20:59 ` Rob Herring
2018-08-07 7:20 ` Christoph Hellwig [this message]
2018-08-08 2:17 ` Palmer Dabbelt
2018-08-08 6:42 ` Atish Patra
2018-08-08 14:16 ` Rob Herring
2018-08-08 15:09 ` Christoph Hellwig
2018-08-08 16:47 ` Marc Zyngier
2018-08-08 16:57 ` Christoph Hellwig
2018-08-09 10:19 ` Marc Zyngier
2018-08-08 19:38 ` Palmer Dabbelt
2018-08-08 23:32 ` Rob Herring
2018-08-09 6:29 ` Palmer Dabbelt
2018-08-09 6:43 ` Christoph Hellwig
2018-08-10 16:57 ` Rob Herring
2018-08-10 20:09 ` Palmer Dabbelt
2018-08-13 14:09 ` Rob Herring
2018-08-02 11:50 ` [PATCH 04/11] RISC-V: remove timer leftovers Christoph Hellwig
2018-08-02 11:50 ` [PATCH 05/11] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-08-02 11:50 ` [PATCH 06/11] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-08-02 11:50 ` [PATCH 07/11] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-08-02 11:50 ` [PATCH 08/11] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-02 11:50 ` [PATCH 09/11] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-08-02 22:19 ` Atish Patra
2018-08-03 12:33 ` Christoph Hellwig
2018-08-04 9:58 ` Christoph Hellwig
2018-08-06 20:34 ` Palmer Dabbelt
2018-08-08 6:47 ` Atish Patra
2018-08-02 11:50 ` [PATCH 10/11] irqchip: add a SiFive PLIC driver Christoph Hellwig
2018-08-02 23:13 ` Atish Patra
2018-08-03 12:29 ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 11/11] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-08-02 23:21 ` Atish Patra
2018-08-03 12:31 ` Christoph Hellwig
2018-08-02 17:24 ` simplified RISC-V interrupt and clocksource handling v2 Palmer Dabbelt
2018-08-03 7:49 ` Thomas Gleixner
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