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From: Rob Herring <robh@kernel.org>
To: Andrea Merello <andrea.merello@gmail.com>
Cc: vkoul@kernel.org, dan.j.williams@intel.com,
	michal.simek@xilinx.com, appana.durga.rao@xilinx.com,
	dmaengine@vger.kernel.org,
	v4-000linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mark.rutland@arm.com,
	devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com
Subject: Re: [PATCH v4 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property
Date: Tue, 7 Aug 2018 08:56:03 -0600	[thread overview]
Message-ID: <20180807145603.GA1664@rob-hp-laptop> (raw)
In-Reply-To: <20180802141012.19970-3-andrea.merello@gmail.com>

On Thu, Aug 02, 2018 at 04:10:08PM +0200, Andrea Merello wrote:
> The width of the "length register" cannot be autodetected, and it is now
> specified with a DT property. Add DOC for it.
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: devicetree@vger.kernel.org
> Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> ---
> Changes in v2:
> 	- change property name
> 	- property is now optional
> 	- cc DT maintainer
> Changes in v3:
> 	- reword
> 	- cc DT maintainerS and ML
> Changes in v4:
> 	- specify the unit, the valid range and the default value
> ---
>  Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> index a2b8bfaec43c..aec4a41a03ae 100644
> --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> @@ -41,6 +41,10 @@ Optional properties:
>  - xlnx,include-sg: Tells configured for Scatter-mode in
>  	the hardware.
>  Optional properties for AXI DMA:
> +- xlnx,sg-length-width: Should be set to the width in bits of the length
> +  	register as configured in h/w. Takes values {8...26}. If the property
> +	is missing or invalid then the default value 23 is used. This is the
> +	maximum value that is supported by all IP versions.

If 23 is the max, then why is the range 8-26?

  reply	other threads:[~2018-08-07 14:56 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-02 14:10 [PATCH v4 1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation Andrea Merello
2018-08-02 14:10 ` [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors Andrea Merello
2018-08-27  5:30   ` Vinod
2018-08-29  8:12     ` Andrea Merello
2018-08-30  8:11       ` Andrea Merello
2018-08-30 13:27         ` Vinod
2018-09-03  8:46           ` Andrea Merello
2018-09-03 10:49             ` Vinod
2018-08-02 14:10 ` [PATCH v4 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property Andrea Merello
2018-08-07 14:56   ` Rob Herring [this message]
2018-08-09  6:36     ` Andrea Merello
2018-08-27  5:31   ` Vinod
2018-08-29  8:14     ` Andrea Merello
2018-08-02 14:10 ` [PATCH v4 4/7] dmaengine: xilinx_dma: program hardware supported buffer length Andrea Merello
2018-08-02 14:10 ` [PATCH v4 5/7] dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather Andrea Merello
2018-08-27  5:34   ` Vinod
2018-08-02 14:10 ` [PATCH v4 6/7] dt-bindings: dmaengine: xilinx_dma: drop has-sg property Andrea Merello
2018-08-02 14:10 ` [PATCH v4 7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP Andrea Merello

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