From: Christoph Hellwig <hch@lst.de>
To: robh+dt@kernel.org, Palmer Dabbelt <palmer@sifive.com>
Cc: Christoph Hellwig <hch@lst.de>,
Paul Walmsley <paul.walmsley@sifive.com>,
tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com,
mark.rutland@arm.com, anup@brainfault.org, atish.patra@wdc.com,
devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
shorne@gmail.com
Subject: Re: simplified RISC-V interrupt and clocksource handling v3
Date: Wed, 8 Aug 2018 08:27:25 +0200 [thread overview]
Message-ID: <20180808062725.GA15636@lst.de> (raw)
In-Reply-To: <mhng-d7c67842-dff7-4200-bc2e-c3eed1a0a7bf@palmer-si-x1c4>
[attention Rob: Palmer said he is going to pull it in, and I'd really
like to have your ACK on the DT bindings, can you chime in if
everything is ok for you?]
On Tue, Aug 07, 2018 at 07:23:19PM -0700, Palmer Dabbelt wrote:
> Thanks! Modulo the one device tree issue I replied to in patch 3 this
> looks great! We've already gotten the ACKs to take this through the RISC-V
> tree, so I'm going to put this along with the queued RISC-V patches on our
> for-next branch, including my proposed change for "sifive,plic-1.0" but
> leaving the device tree bindings with #{address,size}-cells=1.
Note that I saw a branch that only has the actual driver patch, this
needs to be in the documentation as well of couse. I don't really
care which name we settle on as long we agree on it, and document it
properly.
prev parent reply other threads:[~2018-08-08 6:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-04 8:23 simplified RISC-V interrupt and clocksource handling v3 Christoph Hellwig
2018-08-04 8:23 ` [PATCH 1/8] RISC-V: remove timer leftovers Christoph Hellwig
2018-08-04 8:23 ` [PATCH 2/8] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-08-04 8:23 ` [PATCH 3/8] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-08-04 8:23 ` [PATCH 4/8] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-08-04 8:23 ` [PATCH 5/8] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-04 8:23 ` [PATCH 6/8] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-08 14:29 ` Rob Herring
2018-08-08 15:04 ` Christoph Hellwig
2018-08-08 16:15 ` Rob Herring
2018-08-08 16:41 ` Christoph Hellwig
2018-08-08 20:49 ` Palmer Dabbelt
2018-08-04 8:23 ` [PATCH 7/8] irqchip: add a SiFive PLIC driver Christoph Hellwig
2018-08-06 20:27 ` Atish Patra
2018-08-04 8:23 ` [PATCH 8/8] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-08-08 2:23 ` simplified RISC-V interrupt and clocksource handling v3 Palmer Dabbelt
2018-08-08 6:27 ` Christoph Hellwig [this message]
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