From: Christoph Hellwig <hch@lst.de>
To: Rob Herring <robh+dt@kernel.org>
Cc: Christoph Hellwig <hch@lst.de>,
Thomas Gleixner <tglx@linutronix.de>,
Palmer Dabbelt <palmer@sifive.com>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Anup Patel <anup@brainfault.org>,
atish.patra@wdc.com, devicetree@vger.kernel.org,
Albert Ou <aou@eecs.berkeley.edu>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
linux-riscv@lists.infradead.org,
Stafford Horne <shorne@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 6/8] dt-bindings: interrupt-controller: RISC-V PLIC documentation
Date: Wed, 8 Aug 2018 17:04:48 +0200 [thread overview]
Message-ID: <20180808150448.GA31785@lst.de> (raw)
In-Reply-To: <CAL_JsqKKCPhb1um_+68ya0ng_v2tSb5O+-8RQPqx7Od3sJ4FuA@mail.gmail.com>
On Wed, Aug 08, 2018 at 08:29:50AM -0600, Rob Herring wrote:
> Version numbers on the individual patches would be nice...
We've never done these in the subsystems I'm involved with. Too
much clutter in the subject lines for information that is easily
deductable.
> > +Example:
> > +
> > + plic: interrupt-controller@c000000 {
> > + #address-cells = <0>;
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,plic0";
> > + interrupt-controller;
> > + interrupts-extended = <
> > + &cpu0-intc 11
> > + &cpu1-intc 11 &cpu1-intc 9
> > + &cpu2-intc 11 &cpu2-intc 9
> > + &cpu3-intc 11 &cpu3-intc 9
> > + &cpu4-intc 11 &cpu4-intc 9>;
>
> I'm confused why this is still here if you are dropping the cpu intc binding?
We need some parent that identifies the core (hart in RISC-V terminology).
The way the code now works is that it just walks up the parent chain
until it finds a CPU node, so it either accepts the legacy intc node
inbetween, or it accepts the cpu node directly as the intc node is pointless.
I guess for the documentation we should instead just point to the
"riscv" cpu nodes instead?
> I also noticed the cpu binding refers to "riscv,cpu-intc" as well.
> That needs to be fixed too if there's a change.
Only in the examples. I'd be fine with dropping them, but let's keep
that separate from the interrupt support.
next prev parent reply other threads:[~2018-08-08 15:04 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-04 8:23 simplified RISC-V interrupt and clocksource handling v3 Christoph Hellwig
2018-08-04 8:23 ` [PATCH 1/8] RISC-V: remove timer leftovers Christoph Hellwig
2018-08-04 8:23 ` [PATCH 2/8] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-08-04 8:23 ` [PATCH 3/8] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-08-04 8:23 ` [PATCH 4/8] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-08-04 8:23 ` [PATCH 5/8] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-04 8:23 ` [PATCH 6/8] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-08 14:29 ` Rob Herring
2018-08-08 15:04 ` Christoph Hellwig [this message]
2018-08-08 16:15 ` Rob Herring
2018-08-08 16:41 ` Christoph Hellwig
2018-08-08 20:49 ` Palmer Dabbelt
2018-08-04 8:23 ` [PATCH 7/8] irqchip: add a SiFive PLIC driver Christoph Hellwig
2018-08-06 20:27 ` Atish Patra
2018-08-04 8:23 ` [PATCH 8/8] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-08-08 2:23 ` simplified RISC-V interrupt and clocksource handling v3 Palmer Dabbelt
2018-08-08 6:27 ` Christoph Hellwig
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