From: Christoph Hellwig <hch@lst.de>
To: Rob Herring <robh+dt@kernel.org>
Cc: Christoph Hellwig <hch@lst.de>,
Mark Rutland <mark.rutland@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Palmer Dabbelt <palmer@sifive.com>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Anup Patel <anup@brainfault.org>,
atish.patra@wdc.com, devicetree@vger.kernel.org,
Albert Ou <aou@eecs.berkeley.edu>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
linux-riscv@lists.infradead.org,
Stafford Horne <shorne@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 6/8] dt-bindings: interrupt-controller: RISC-V PLIC documentation
Date: Wed, 8 Aug 2018 18:41:27 +0200 [thread overview]
Message-ID: <20180808164127.GA5733@lst.de> (raw)
In-Reply-To: <CAL_JsqKgawQA5V2W1e9QFb_Ri+Aka-08WizeSD9kdxyBdcwpEQ@mail.gmail.com>
On Wed, Aug 08, 2018 at 10:15:58AM -0600, Rob Herring wrote:
> 'interrupts' (via
> interrupt-parent) or 'interrupts-extended' has to point to an
> 'interrupt-controller' node. I guess you could make the cpu nodes
> interrupt-controllers. That's a bit strange, but I can't think of a
> reason why that wouldn't work.
It could work, and would actually match how the hardware works
fairly closely.
> Just because the cpu-intc is not made to be an irqchip in the kernel
> doesn't mean it can't still be represented as an interrupt-controller
> in DT. It shouldn't be designed just around how some OS happens to
> implement things.
Independent of how you implement it, there isn't really such a thing
as the cpu-intc. The CPU itself has a number of exceptions, that
are all handled the same way. One of them just happens to be
the connection to an external interrupt controller.
That being said I'm fine with keeping up the pretence (at least in
DT) that it is a separate entity and resubmit the cpu-intc docs
given how widespread they exist already.
next prev parent reply other threads:[~2018-08-08 16:41 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-04 8:23 simplified RISC-V interrupt and clocksource handling v3 Christoph Hellwig
2018-08-04 8:23 ` [PATCH 1/8] RISC-V: remove timer leftovers Christoph Hellwig
2018-08-04 8:23 ` [PATCH 2/8] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-08-04 8:23 ` [PATCH 3/8] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-08-04 8:23 ` [PATCH 4/8] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-08-04 8:23 ` [PATCH 5/8] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-04 8:23 ` [PATCH 6/8] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-08 14:29 ` Rob Herring
2018-08-08 15:04 ` Christoph Hellwig
2018-08-08 16:15 ` Rob Herring
2018-08-08 16:41 ` Christoph Hellwig [this message]
2018-08-08 20:49 ` Palmer Dabbelt
2018-08-04 8:23 ` [PATCH 7/8] irqchip: add a SiFive PLIC driver Christoph Hellwig
2018-08-06 20:27 ` Atish Patra
2018-08-04 8:23 ` [PATCH 8/8] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-08-08 2:23 ` simplified RISC-V interrupt and clocksource handling v3 Palmer Dabbelt
2018-08-08 6:27 ` Christoph Hellwig
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