From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Cercueil Subject: [PATCH v7 22/24] MIPS: CI20: Reduce system timer and clocksource to 3 MHz Date: Tue, 21 Aug 2018 19:18:46 +0200 Message-ID: <20180821171846.23050-1-paul@crapouillou.net> References: <20180821171635.22740-1-paul@crapouillou.net> Return-path: In-Reply-To: <20180821171635.22740-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org To: Thomas Gleixner , Daniel Lezcano , Rob Herring , Thierry Reding , Mark Rutland , Ralf Baechle , Paul Burton , Jonathan Corbet Cc: od@zcrc.me, Mathieu Malaterre , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-mips@linux-mips.org, linux-doc@vger.kernel.org, linux-clk@vger.kernel.org, Paul Cercueil List-Id: devicetree@vger.kernel.org The default clock (48 MHz) is too fast for the system timer, which fails to report time accurately. Signed-off-by: Paul Cercueil --- Notes: v5: New patch v6: Set also the rate for the clocksource channel's clock v7: No change arch/mips/boot/dts/ingenic/ci20.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 50cff3cbcc6d..f64d32443097 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -238,3 +238,9 @@ bias-disable; }; }; + +&tcu { + /* 3 MHz for the system timer and clocksource */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; + assigned-clock-rates = <3000000>, <3000000>; +}; -- 2.11.0