From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>, Andrew Lunn <andrew@lunn.ch>,
Jason Cooper <jason@lakedaemon.net>,
devicetree@vger.kernel.org,
Antoine Tenart <antoine.tenart@bootlin.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Gregory Clement <gregory.clement@bootlin.com>,
Haim Boot <hayim@marvell.com>, Will Deacon <will.deacon@arm.com>,
Maxime Chevallier <maxime.chevallier@bootlin.com>,
Nadav Haklai <nadavh@marvell.com>,
Rob Herring <robh+dt@kernel.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Thomas Gleixner <tglx@linutronix.de>,
Hanna Hawa <hannah@marvell.com>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v4 09/14] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI)
Date: Thu, 23 Aug 2018 13:44:10 +0200 [thread overview]
Message-ID: <20180823134410.2df84fa4@xps13> (raw)
In-Reply-To: <9c3168e2-3653-5359-7ddb-9e6ac1b47bb8@arm.com>
Hi Marc,
Marc Zyngier <marc.zyngier@arm.com> wrote on Tue, 21 Aug 2018 11:37:47
+0100:
> On 21/08/18 11:28, Miquel Raynal wrote:
> > Hi Marc,
> >
> > Marc Zyngier <marc.zyngier@arm.com> wrote on Tue, 21 Aug 2018 10:19:04
> > +0100:
> >
> >> On 21/08/18 10:08, Miquel Raynal wrote:
> >>> Hi Marc,
> >>>
> >>> I'm fine with the rest of the comments, please find just one last
> >>> question below.
> >>>
> >>> [...]
> >>>
> >>>>> @@ -133,12 +164,36 @@ mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
> >>>>> return -EINVAL;
> >>>>> }
> >>>>>
> >>>>> - /* Mask the type to prevent wrong DT configuration */
> >>>>> - *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
> >>>>> + /*
> >>>>> + * The ICU receives level-interrupts. MSI SEI are
> >>>>> + * edge-interrupts while MSI NSR are level-interrupts. Update the type
> >>>>> + * accordingly for the parent irqchip.
> >>>>> + */
> >>>>> + if (msi_data->subset_data->icu_group == ICU_GRP_SEI)
> >>>>> + *type = IRQ_TYPE_EDGE_RISING;
> >>>>
> >>>> That's interesting. How is the resampling done here?
> >>>
> >>> I'm not sure to understand the question. What does 'resampling' means
> >>> in such context? MSI SEIs are of type "edge" and use the traditional
> >>> MSI signalling infrastructure. I'm asking to be sure not to ignore
> >>> something wrong in my code.
> >>
> >> You seems to be turning a level interrupt into an edge.
> >
> > If is an SEI interrupt, it cannot be a level interrupt and the type
> > will be IRQ_TYPE_EDGE_RISING.
> >
> >> You can do that,
> >> but only if you resample the level on EOI (and regenerate the
> >> corresponding edge if the level is still high).
> >
> > What is before is a '& IRQ_TYPE_SENSE_MASK' operation. In theory,
> > *type could be anything of IRQ_TYPE_{EDGE,LEVEL}_* at this moment. But,
> > as stated above, it cannot be anything else than IRQ_TYPE_EDGE_RISING.
> > I thought more clear to enforce it but if this unclear and useless,
> > let's drop it?
>
> I think overriding the trigger that way is very confusing. Either it
> comes from DT, or it comes from the MSI framwork. In both cases, it has
> to be correct, and overriding it is just papering over other bugs.
>
> I'd rather you put a WARN_ON if you encounter an illegal interrupt trigger.
Actually I do remember now why I enforced the type:
Let's say my thermal IP in a CP110 triggers an interrupt. This
interrupt is of type LEVEL_HIGH, and it is declared in the DT as:
thermal: thermal-sensor@... {
[...]
interrupts-extended = <&icu_sei 116 IRQ_TYPE_LEVEL_HIGH>;
};
The ICU callback ->translate() will be called with fwspec being the C
view of the above "interrupts-extended" property, so the interrupt type
will be LEVEL_HIGH.
However, the "icu_sei" parent is the SEI IP in the AP806 and this IP
only receives edge interrupts. What happens is that the SEI's
->set_type() callback is called with LEVEL_HIGH type (while it
only supports EDGE_RISING interrupts) and I want the driver to throw an
error in this case.
My way of handling this was to force *type to be EDGE_RISING in the ICU
->translate() callback whenever an SEI was triggered. As this seems not
to be correct, how would you handle such situation?
Thanks,
Miquèl
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next prev parent reply other threads:[~2018-08-23 11:44 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-05 12:39 [PATCH v4 00/14] Add System Error Interrupt support to Armada SoCs Miquel Raynal
2018-07-05 12:39 ` [PATCH v4 01/14] genirq/msi: Allow creation of a tree-based irqdomain for platform-msi Miquel Raynal
2018-07-05 12:39 ` [PATCH v4 02/14] dt-bindings/interrupt-controller: fix Marvell ICU length in the example Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 03/14] irqchip/irq-mvebu-icu: fix wrong private data retrieval Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 04/14] irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 05/14] irqchip/irq-mvebu-icu: disociate ICU and NSR Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 06/14] irqchip/irq-mvebu-icu: support ICU subnodes Miquel Raynal
2018-08-20 14:16 ` Marc Zyngier
2018-07-05 12:40 ` [PATCH v4 07/14] irqchip/irq-mvebu-sei: add new driver for Marvell SEI Miquel Raynal
2018-08-20 14:58 ` Marc Zyngier
2018-07-05 12:40 ` [PATCH v4 08/14] arm64: marvell: enable SEI driver Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 09/14] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) Miquel Raynal
2018-08-20 15:21 ` Marc Zyngier
2018-08-21 9:08 ` Miquel Raynal
2018-08-21 9:19 ` Marc Zyngier
2018-08-21 10:28 ` Miquel Raynal
2018-08-21 10:37 ` Marc Zyngier
2018-08-21 15:41 ` Miquel Raynal
2018-08-23 11:44 ` Miquel Raynal [this message]
2018-07-05 12:40 ` [PATCH v4 10/14] dt-bindings/interrupt-controller: update Marvell ICU bindings Miquel Raynal
2018-07-16 15:27 ` Rob Herring
2018-07-16 16:39 ` Miquel Raynal
2018-07-16 17:44 ` Rob Herring
2018-07-16 19:30 ` Thomas Petazzoni
2018-07-16 19:38 ` Thomas Petazzoni
2018-07-05 12:40 ` [PATCH v4 11/14] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 12/14] arm64: dts: marvell: add AP806 SEI subnode Miquel Raynal
2018-07-16 15:31 ` Rob Herring
2018-07-05 12:40 ` [PATCH v4 13/14] arm64: dts: marvell: use new bindings for CP110 interrupts Miquel Raynal
2018-07-05 12:40 ` [PATCH v4 14/14] arm64: dts: marvell: add CP110 ICU SEI subnode Miquel Raynal
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