* [PATCH 1/5] arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes
2018-08-23 8:58 [PATCH 0/5] Add SYS-DMAC/INTC-EX/[H]SCIF/EAVB/RWDT support Biju Das
@ 2018-08-23 8:58 ` Biju Das
2018-08-24 8:38 ` Simon Horman
2018-08-23 8:58 ` [PATCH 2/5] arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes Biju Das
` (3 subsequent siblings)
4 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2018-08-23 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon
Cc: Fabrizio Castro, devicetree, Chris Paterson, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-renesas-soc, Simon Horman,
linux-arm-kernel
Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 102 ++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 8e63e9a..4a4cf35 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,108 @@
#power-domain-cells = <1>;
};
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a774a1",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x10000>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ dmac1: dma-controller@e7300000 {
+ compatible = "renesas,dmac-r8a774a1",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ dmac2: dma-controller@e7310000 {
+ compatible = "renesas,dmac-r8a774a1",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 217>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 217>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 1/5] arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes
2018-08-23 8:58 ` [PATCH 1/5] arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes Biju Das
@ 2018-08-24 8:38 ` Simon Horman
2018-08-30 12:14 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2018-08-24 8:38 UTC (permalink / raw)
To: Biju Das
Cc: Mark Rutland, devicetree, Chris Paterson, Magnus Damm,
Geert Uytterhoeven, Catalin Marinas, Will Deacon,
linux-renesas-soc, Rob Herring, Fabrizio Castro, linux-arm-kernel
On Thu, Aug 23, 2018 at 09:58:47AM +0100, Biju Das wrote:
> Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/5] arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes
2018-08-24 8:38 ` Simon Horman
@ 2018-08-30 12:14 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-08-30 12:14 UTC (permalink / raw)
To: Biju Das
Cc: Mark Rutland, devicetree, Chris Paterson, Magnus Damm,
Geert Uytterhoeven, Catalin Marinas, Will Deacon,
linux-renesas-soc, Rob Herring, Fabrizio Castro, linux-arm-kernel
On Fri, Aug 24, 2018 at 10:38:59AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 09:58:47AM +0100, Biju Das wrote:
> > Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Thanks,
>
> This looks fine to me but I will wait to see if there are other reviews
> before applying.
Thanks again, applied for v4.20.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/5] arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
2018-08-23 8:58 [PATCH 0/5] Add SYS-DMAC/INTC-EX/[H]SCIF/EAVB/RWDT support Biju Das
2018-08-23 8:58 ` [PATCH 1/5] arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes Biju Das
@ 2018-08-23 8:58 ` Biju Das
2018-08-24 8:52 ` Simon Horman
2018-08-23 8:58 ` [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add INTC-EX device node Biju Das
` (2 subsequent siblings)
4 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2018-08-23 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon
Cc: Fabrizio Castro, devicetree, Chris Paterson, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-renesas-soc, Simon Horman,
linux-arm-kernel
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
incl. clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 185 ++++++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 4a4cf35..81fba7f 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,94 @@
#power-domain-cells = <1>;
};
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a774a1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a774a1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a774a1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a774a1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ hscif4: serial@e66b0000 {
+ compatible = "renesas,hscif-r8a774a1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66b0000 0 0x60>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 516>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a774a1",
"renesas,rcar-dmac";
@@ -246,6 +334,103 @@
dma-channels = <16>;
};
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a774a1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a774a1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a774a1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e88000 0 0x40>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 310>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a774a1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a774a1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6f30000 {
+ compatible = "renesas,scif-r8a774a1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6f30000 0 0x40>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ <&dmac2 0x5b>, <&dmac2 0x5a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 2/5] arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
2018-08-23 8:58 ` [PATCH 2/5] arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes Biju Das
@ 2018-08-24 8:52 ` Simon Horman
2018-08-30 12:15 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2018-08-24 8:52 UTC (permalink / raw)
To: Biju Das
Cc: Mark Rutland, Fabrizio Castro, Chris Paterson, Magnus Damm,
Geert Uytterhoeven, devicetree, Catalin Marinas, Will Deacon,
linux-renesas-soc, Rob Herring, linux-arm-kernel
On Thu, Aug 23, 2018 at 09:58:48AM +0100, Biju Das wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
> incl. clocks, power domains and DMAs.
> According to the HW user manual, SCIF[015] and HSCIF[012] are
> connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
> HSCIF[34] are connected to SYS-DMAC0.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/5] arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
2018-08-24 8:52 ` Simon Horman
@ 2018-08-30 12:15 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-08-30 12:15 UTC (permalink / raw)
To: Biju Das
Cc: Mark Rutland, Fabrizio Castro, Chris Paterson, Magnus Damm,
Geert Uytterhoeven, devicetree, Catalin Marinas, Will Deacon,
linux-renesas-soc, Rob Herring, linux-arm-kernel
On Fri, Aug 24, 2018 at 10:52:57AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 09:58:48AM +0100, Biju Das wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
> > incl. clocks, power domains and DMAs.
> > According to the HW user manual, SCIF[015] and HSCIF[012] are
> > connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
> > HSCIF[34] are connected to SYS-DMAC0.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Thanks,
>
> This looks fine to me but I will wait to see if there are other reviews
> before applying.
Thanks again, applied for v4.20.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add INTC-EX device node
2018-08-23 8:58 [PATCH 0/5] Add SYS-DMAC/INTC-EX/[H]SCIF/EAVB/RWDT support Biju Das
2018-08-23 8:58 ` [PATCH 1/5] arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes Biju Das
2018-08-23 8:58 ` [PATCH 2/5] arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes Biju Das
@ 2018-08-23 8:58 ` Biju Das
2018-08-24 8:55 ` Simon Horman
2018-08-23 8:58 ` [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node Biju Das
2018-08-23 8:58 ` [PATCH 5/5] arm64: dts: renesas: r8a774a1: Add RWDT node Biju Das
4 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2018-08-23 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon
Cc: Fabrizio Castro, devicetree, Chris Paterson, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-renesas-soc, Simon Horman,
linux-arm-kernel
Add support for the Interrupt Controller for External Devices
(INTC-EX) on RZ/G2M.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 81fba7f..15d7785 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,22 @@
#power-domain-cells = <1>;
};
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 407>;
+ };
+
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a774a1",
"renesas,rcar-gen3-hscif",
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add INTC-EX device node
2018-08-23 8:58 ` [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add INTC-EX device node Biju Das
@ 2018-08-24 8:55 ` Simon Horman
2018-08-30 12:15 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2018-08-24 8:55 UTC (permalink / raw)
To: Biju Das
Cc: Mark Rutland, devicetree, Chris Paterson, Magnus Damm,
Geert Uytterhoeven, Catalin Marinas, Will Deacon,
linux-renesas-soc, Rob Herring, Fabrizio Castro, linux-arm-kernel
On Thu, Aug 23, 2018 at 09:58:49AM +0100, Biju Das wrote:
> Add support for the Interrupt Controller for External Devices
> (INTC-EX) on RZ/G2M.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add INTC-EX device node
2018-08-24 8:55 ` Simon Horman
@ 2018-08-30 12:15 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-08-30 12:15 UTC (permalink / raw)
To: Biju Das
Cc: Mark Rutland, devicetree, Chris Paterson, Magnus Damm,
Geert Uytterhoeven, Catalin Marinas, Will Deacon,
linux-renesas-soc, Rob Herring, Fabrizio Castro, linux-arm-kernel
On Fri, Aug 24, 2018 at 10:55:13AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 09:58:49AM +0100, Biju Das wrote:
> > Add support for the Interrupt Controller for External Devices
> > (INTC-EX) on RZ/G2M.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Thanks,
>
> This looks fine to me but I will wait to see if there are other reviews
> before applying.
Thanks again, applied for v4.20.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
2018-08-23 8:58 [PATCH 0/5] Add SYS-DMAC/INTC-EX/[H]SCIF/EAVB/RWDT support Biju Das
` (2 preceding siblings ...)
2018-08-23 8:58 ` [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add INTC-EX device node Biju Das
@ 2018-08-23 8:58 ` Biju Das
2018-08-24 9:03 ` Simon Horman
2018-08-23 8:58 ` [PATCH 5/5] arm64: dts: renesas: r8a774a1: Add RWDT node Biju Das
4 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2018-08-23 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon
Cc: Fabrizio Castro, devicetree, Chris Paterson, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-renesas-soc, Simon Horman,
linux-arm-kernel
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
This patch adds the SoC specific part of the Ethernet AVB
device tree node.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 15d7785..b771211 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -350,6 +350,51 @@
dma-channels = <16>;
};
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a774a1",
+ "renesas,etheravb-rcar-gen3";
+ reg = <0 0xe6800000 0 0x800>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a774a1",
"renesas,rcar-gen3-scif", "renesas,scif";
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
2018-08-23 8:58 ` [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node Biju Das
@ 2018-08-24 9:03 ` Simon Horman
2018-08-24 9:06 ` Fabrizio Castro
0 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2018-08-24 9:03 UTC (permalink / raw)
To: Biju Das
Cc: Mark Rutland, Fabrizio Castro, Chris Paterson, Magnus Damm,
Geert Uytterhoeven, devicetree, Catalin Marinas, Will Deacon,
linux-renesas-soc, Rob Herring, linux-arm-kernel
On Thu, Aug 23, 2018 at 09:58:50AM +0100, Biju Das wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> This patch adds the SoC specific part of the Ethernet AVB
> device tree node.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> ---
> arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> index 15d7785..b771211 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> @@ -350,6 +350,51 @@
> dma-channels = <16>;
> };
>
> + avb: ethernet@e6800000 {
> + compatible = "renesas,etheravb-r8a774a1",
> + "renesas,etheravb-rcar-gen3";
> + reg = <0 0xe6800000 0 0x800>;
Should a region, <0 0xe6a00000 0 0x10000>, also be added
here to describe the suggested space for descriptors?
Otherwise the patch looks good to me.
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15",
> + "ch16", "ch17", "ch18", "ch19",
> + "ch20", "ch21", "ch22", "ch23",
> + "ch24";
> + clocks = <&cpg CPG_MOD 812>;
> + power-domains = <&sysc 32>;
> + resets = <&cpg 812>;
> + phy-mode = "rgmii";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> scif0: serial@e6e60000 {
> compatible = "renesas,scif-r8a774a1",
> "renesas,rcar-gen3-scif", "renesas,scif";
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
2018-08-24 9:03 ` Simon Horman
@ 2018-08-24 9:06 ` Fabrizio Castro
2018-08-28 12:20 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Fabrizio Castro @ 2018-08-24 9:06 UTC (permalink / raw)
To: Simon Horman, Biju Das
Cc: Mark Rutland, devicetree@vger.kernel.org, Chris Paterson,
Magnus Damm, Geert Uytterhoeven, Catalin Marinas, Will Deacon,
linux-renesas-soc@vger.kernel.org, Rob Herring,
linux-arm-kernel@lists.infradead.org
Hello Simon,
Thank you for your feedback!
> Subject: Re: [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
>
> On Thu, Aug 23, 2018 at 09:58:50AM +0100, Biju Das wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > This patch adds the SoC specific part of the Ethernet AVB
> > device tree node.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> > ---
> > arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++++++++++++++++++++++++++++++
> > 1 file changed, 45 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > index 15d7785..b771211 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > @@ -350,6 +350,51 @@
> > dma-channels = <16>;
> > };
> >
> > +avb: ethernet@e6800000 {
> > +compatible = "renesas,etheravb-r8a774a1",
> > + "renesas,etheravb-rcar-gen3";
> > +reg = <0 0xe6800000 0 0x800>;
>
> Should a region, <0 0xe6a00000 0 0x10000>, also be added
> here to describe the suggested space for descriptors?
There is no STBE (Stream Buffer for EthernetAVB-IF) on the r8a774a1, and that's why this node doesn't come with such a region.
Thanks,
Fab
>
> Otherwise the patch looks good to me.
>
> > +interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> > +interrupt-names = "ch0", "ch1", "ch2", "ch3",
> > + "ch4", "ch5", "ch6", "ch7",
> > + "ch8", "ch9", "ch10", "ch11",
> > + "ch12", "ch13", "ch14", "ch15",
> > + "ch16", "ch17", "ch18", "ch19",
> > + "ch20", "ch21", "ch22", "ch23",
> > + "ch24";
> > +clocks = <&cpg CPG_MOD 812>;
> > +power-domains = <&sysc 32>;
> > +resets = <&cpg 812>;
> > +phy-mode = "rgmii";
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +status = "disabled";
> > +};
> > +
> > scif0: serial@e6e60000 {
> > compatible = "renesas,scif-r8a774a1",
> > "renesas,rcar-gen3-scif", "renesas,scif";
> > --
> > 2.7.4
> >
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
2018-08-24 9:06 ` Fabrizio Castro
@ 2018-08-28 12:20 ` Simon Horman
2018-08-30 12:16 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2018-08-28 12:20 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Mark Rutland, devicetree@vger.kernel.org, Chris Paterson,
Magnus Damm, Geert Uytterhoeven, Catalin Marinas, Will Deacon,
Biju Das, linux-renesas-soc@vger.kernel.org, Rob Herring,
linux-arm-kernel@lists.infradead.org
On Fri, Aug 24, 2018 at 09:06:49AM +0000, Fabrizio Castro wrote:
> Hello Simon,
>
> Thank you for your feedback!
>
> > Subject: Re: [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
> >
> > On Thu, Aug 23, 2018 at 09:58:50AM +0100, Biju Das wrote:
> > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > This patch adds the SoC specific part of the Ethernet AVB
> > > device tree node.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> > > ---
> > > arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++++++++++++++++++++++++++++++
> > > 1 file changed, 45 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > > index 15d7785..b771211 100644
> > > --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > > @@ -350,6 +350,51 @@
> > > dma-channels = <16>;
> > > };
> > >
> > > +avb: ethernet@e6800000 {
> > > +compatible = "renesas,etheravb-r8a774a1",
> > > + "renesas,etheravb-rcar-gen3";
> > > +reg = <0 0xe6800000 0 0x800>;
> >
> > Should a region, <0 0xe6a00000 0 0x10000>, also be added
> > here to describe the suggested space for descriptors?
>
> There is no STBE (Stream Buffer for EthernetAVB-IF) on the r8a774a1, and that's why this node doesn't come with such a region.
Thanks for the follow-up. In that case I'm fine with this patch but
I'd like to wait a little longer to allow review by others.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
2018-08-28 12:20 ` Simon Horman
@ 2018-08-30 12:16 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-08-30 12:16 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Mark Rutland, devicetree@vger.kernel.org, Chris Paterson,
Magnus Damm, Geert Uytterhoeven, Catalin Marinas, Will Deacon,
Biju Das, linux-renesas-soc@vger.kernel.org, Rob Herring,
linux-arm-kernel@lists.infradead.org
On Tue, Aug 28, 2018 at 02:20:44PM +0200, Simon Horman wrote:
> On Fri, Aug 24, 2018 at 09:06:49AM +0000, Fabrizio Castro wrote:
> > Hello Simon,
> >
> > Thank you for your feedback!
> >
> > > Subject: Re: [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
> > >
> > > On Thu, Aug 23, 2018 at 09:58:50AM +0100, Biju Das wrote:
> > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > >
> > > > This patch adds the SoC specific part of the Ethernet AVB
> > > > device tree node.
> > > >
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> > > > ---
> > > > arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++++++++++++++++++++++++++++++
> > > > 1 file changed, 45 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > > > index 15d7785..b771211 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > > > @@ -350,6 +350,51 @@
> > > > dma-channels = <16>;
> > > > };
> > > >
> > > > +avb: ethernet@e6800000 {
> > > > +compatible = "renesas,etheravb-r8a774a1",
> > > > + "renesas,etheravb-rcar-gen3";
> > > > +reg = <0 0xe6800000 0 0x800>;
> > >
> > > Should a region, <0 0xe6a00000 0 0x10000>, also be added
> > > here to describe the suggested space for descriptors?
> >
> > There is no STBE (Stream Buffer for EthernetAVB-IF) on the r8a774a1, and that's why this node doesn't come with such a region.
>
> Thanks for the follow-up. In that case I'm fine with this patch but
> I'd like to wait a little longer to allow review by others.
Thanks again, applied for v4.20.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/5] arm64: dts: renesas: r8a774a1: Add RWDT node
2018-08-23 8:58 [PATCH 0/5] Add SYS-DMAC/INTC-EX/[H]SCIF/EAVB/RWDT support Biju Das
` (3 preceding siblings ...)
2018-08-23 8:58 ` [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node Biju Das
@ 2018-08-23 8:58 ` Biju Das
2018-08-24 9:05 ` Simon Horman
4 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2018-08-23 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon
Cc: Fabrizio Castro, devicetree, Chris Paterson, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-renesas-soc, Simon Horman,
linux-arm-kernel
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b771211..b9a3818 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -123,6 +123,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a774a1-wdt",
+ "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a774a1-cpg-mssr";
reg = <0 0xe6150000 0 0x0bb0>;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 5/5] arm64: dts: renesas: r8a774a1: Add RWDT node
2018-08-23 8:58 ` [PATCH 5/5] arm64: dts: renesas: r8a774a1: Add RWDT node Biju Das
@ 2018-08-24 9:05 ` Simon Horman
2018-08-30 12:16 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2018-08-24 9:05 UTC (permalink / raw)
To: Biju Das
Cc: Mark Rutland, devicetree, Chris Paterson, Magnus Damm,
Geert Uytterhoeven, Catalin Marinas, Will Deacon,
linux-renesas-soc, Rob Herring, Fabrizio Castro, linux-arm-kernel
On Thu, Aug 23, 2018 at 09:58:51AM +0100, Biju Das wrote:
> Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
> RZ/G2M (r8a774a1) SoC.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
> arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/5] arm64: dts: renesas: r8a774a1: Add RWDT node
2018-08-24 9:05 ` Simon Horman
@ 2018-08-30 12:16 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-08-30 12:16 UTC (permalink / raw)
To: Biju Das
Cc: Mark Rutland, devicetree, Chris Paterson, Magnus Damm,
Geert Uytterhoeven, Catalin Marinas, Will Deacon,
linux-renesas-soc, Rob Herring, Fabrizio Castro, linux-arm-kernel
On Fri, Aug 24, 2018 at 11:05:03AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 09:58:51AM +0100, Biju Das wrote:
> > Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
> > RZ/G2M (r8a774a1) SoC.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > ---
> > arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
>
> Thanks,
>
> This looks fine to me but I will wait to see if there are other reviews
> before applying.
Thanks again, applied for v4.20.
^ permalink raw reply [flat|nested] 18+ messages in thread