From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Cc: devicetree@vger.kernel.org, slongerbeam@gmail.com,
niklas.soderlund@ragnatech.se, jacopo@jmondi.org
Subject: [PATCH v2 13/23] v4l: fwnode: Support default CSI-2 lane mapping for drivers
Date: Mon, 27 Aug 2018 12:29:50 +0300 [thread overview]
Message-ID: <20180827093000.29165-14-sakari.ailus@linux.intel.com> (raw)
In-Reply-To: <20180827093000.29165-1-sakari.ailus@linux.intel.com>
Most hardware doesn't support re-mapping of the CSI-2 lanes. Especially
sensor drivers have a default number of lanes. Instead of requiring the
caller (the driver) to provide such a unit mapping, provide one if no
mapping is configured.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/v4l2-core/v4l2-fwnode.c | 60 +++++++++++++++++++++++++++--------
1 file changed, 46 insertions(+), 14 deletions(-)
diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c
index 282595c90818..0ddf05bb589a 100644
--- a/drivers/media/v4l2-core/v4l2-fwnode.c
+++ b/drivers/media/v4l2-core/v4l2-fwnode.c
@@ -47,20 +47,35 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode,
enum v4l2_fwnode_bus_type bus_type)
{
struct v4l2_fwnode_bus_mipi_csi2 *bus = &vep->bus.mipi_csi2;
- bool have_clk_lane = false, have_lane_polarities = false;
+ bool have_clk_lane = false, have_data_lanes = false,
+ have_lane_polarities = false;
unsigned int flags = 0, lanes_used = 0;
u32 array[1 + V4L2_FWNODE_CSI2_MAX_DATA_LANES];
+ u32 clock_lane = 0;
unsigned int num_data_lanes = 0;
+ bool use_default_lane_mapping = false;
unsigned int i;
u32 v;
int rval;
if (bus_type == V4L2_FWNODE_BUS_TYPE_CSI2_DPHY) {
+ use_default_lane_mapping = true;
+
num_data_lanes = min_t(u32, bus->num_data_lanes,
V4L2_FWNODE_CSI2_MAX_DATA_LANES);
- for (i = 0; i < num_data_lanes; i++)
+ clock_lane = bus->clock_lane;
+ if (clock_lane)
+ use_default_lane_mapping = false;
+
+ for (i = 0; i < num_data_lanes; i++) {
array[i] = bus->data_lanes[i];
+ if (array[i])
+ use_default_lane_mapping = false;
+ }
+
+ if (use_default_lane_mapping)
+ pr_debug("using default lane mapping\n");
}
rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
@@ -70,15 +85,21 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode,
fwnode_property_read_u32_array(fwnode, "data-lanes", array,
num_data_lanes);
+
+ have_data_lanes = true;
}
for (i = 0; i < num_data_lanes; i++) {
- if (lanes_used & BIT(array[i]))
- pr_warn("duplicated lane %u in data-lanes\n",
- array[i]);
+ if (lanes_used & BIT(array[i])) {
+ if (have_data_lanes || !use_default_lane_mapping)
+ pr_warn("duplicated lane %u in data-lanes, using defaults\n",
+ array[i]);
+ use_default_lane_mapping = true;
+ }
lanes_used |= BIT(array[i]);
- pr_debug("lane %u position %u\n", i, array[i]);
+ if (have_data_lanes)
+ pr_debug("lane %u position %u\n", i, array[i]);
}
rval = fwnode_property_read_u32_array(fwnode, "lane-polarities", NULL,
@@ -94,13 +115,16 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode,
}
if (!fwnode_property_read_u32(fwnode, "clock-lanes", &v)) {
- if (lanes_used & BIT(v))
- pr_warn("duplicated lane %u in clock-lanes\n", v);
- lanes_used |= BIT(v);
-
- bus->clock_lane = v;
- have_clk_lane = true;
+ clock_lane = v;
pr_debug("clock lane position %u\n", v);
+ have_clk_lane = true;
+ }
+
+ if (lanes_used & BIT(clock_lane)) {
+ if (have_clk_lane || !use_default_lane_mapping)
+ pr_warn("duplicated lane %u in clock-lanes, using defaults\n",
+ v);
+ use_default_lane_mapping = true;
}
if (fwnode_property_present(fwnode, "clock-noncontinuous")) {
@@ -115,8 +139,16 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode,
bus->flags = flags;
vep->bus_type = V4L2_MBUS_CSI2_DPHY;
bus->num_data_lanes = num_data_lanes;
- for (i = 0; i < num_data_lanes; i++)
- bus->data_lanes[i] = array[i];
+
+ if (use_default_lane_mapping) {
+ bus->clock_lane = 0;
+ for (i = 0; i < num_data_lanes; i++)
+ bus->data_lanes[i] = 1 + i;
+ } else {
+ bus->clock_lane = clock_lane;
+ for (i = 0; i < num_data_lanes; i++)
+ bus->data_lanes[i] = array[i];
+ }
if (have_lane_polarities) {
fwnode_property_read_u32_array(fwnode,
--
2.11.0
next prev parent reply other threads:[~2018-08-27 13:15 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-27 9:29 [PATCH v2 00/23] V4L2 fwnode rework; support for default configuration Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 01/23] v4l: fwnode: Add debug prints for V4L2 endpoint property parsing Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 02/23] v4l: fwnode: Use fwnode_graph_for_each_endpoint Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 03/23] v4l: fwnode: The CSI-2 clock is continuous if it's not non-continuous Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 04/23] dt-bindings: media: Specify bus type for MIPI D-PHY, others, explicitly Sakari Ailus
2018-08-29 0:45 ` Rob Herring
2018-08-27 9:29 ` [PATCH v2 05/23] v4l: fwnode: Add definitions for CSI-2 D-PHY, parallel and Bt.656 busses Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 06/23] v4l: mediabus: Recognise CSI-2 D-PHY and C-PHY Sakari Ailus
2018-08-31 8:02 ` [PATCH v2.1 " Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 07/23] v4l: fwnode: Let the caller provide V4L2 fwnode endpoint Sakari Ailus
2018-09-12 14:51 ` jacopo mondi
2018-09-12 20:46 ` Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 08/23] v4l: fwnode: Detect bus type correctly Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 09/23] v4l: fwnode: Make use of newly specified bus types Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 10/23] v4l: fwnode: Read lane inversion information despite lane numbering Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 11/23] v4l: fwnode: Only assign configuration if there is no error Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 12/23] v4l: fwnode: Support driver-defined lane mapping defaults Sakari Ailus
2018-08-27 9:29 ` Sakari Ailus [this message]
2018-08-27 9:29 ` [PATCH v2 14/23] v4l: fwnode: Parse the graph endpoint as last Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 15/23] v4l: fwnode: Use default parallel flags Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 16/23] v4l: fwnode: Initialise the V4L2 fwnode endpoints to zero Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 17/23] v4l: fwnode: Only zero the struct if bus type is set to V4L2_MBUS_UNKNOWN Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 18/23] v4l: fwnode: Use media bus type for bus parser selection Sakari Ailus
2018-09-12 15:15 ` jacopo mondi
2018-09-12 20:53 ` Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 19/23] v4l: fwnode: Print bus type Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 20/23] v4l: fwnode: Use V4L2 fwnode endpoint media bus type if set Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 21/23] v4l: fwnode: Support parsing of CSI-2 C-PHY endpoints Sakari Ailus
2018-08-27 9:29 ` [PATCH v2 22/23] v4l: fwnode: Update V4L2 fwnode endpoint parsing documentation Sakari Ailus
2018-08-27 9:30 ` [PATCH v2 23/23] smiapp: Query the V4L2 endpoint for a specific bus type Sakari Ailus
2018-08-29 0:53 ` [PATCH v2 00/23] V4L2 fwnode rework; support for default configuration Steve Longerbeam
2018-08-29 12:52 ` Sakari Ailus
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