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* [andriy.shevchenko@linux.intel.com: Re: [PATCH] spi: dw-mmio: add MSCC Jaguar2 support]
@ 2018-08-29 15:09 Andy Shevchenko
  2018-08-29 15:15 ` Mark Brown
  0 siblings, 1 reply; 5+ messages in thread
From: Andy Shevchenko @ 2018-08-29 15:09 UTC (permalink / raw)
  To: Mark Brown
  Cc: linux-spi, devicetree, linux-kernel, Thomas Petazzoni,
	Allan Nielsen, Alexandre Belloni

----- Forwarded message from Andy Shevchenko <andriy.shevchenko@linux.intel.com> -----

Date: Wed, 29 Aug 2018 18:08:31 +0300
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: Re: [PATCH] spi: dw-mmio: add MSCC Jaguar2 support
User-Agent: Mutt/1.10.1 (2018-07-13)

On Wed, Aug 29, 2018 at 02:45:48PM +0200, Alexandre Belloni wrote:
> Unfortunately, the Jaguar2 CPU_SYSTEM_CTRL register set has a different
> layout than the Ocelot one. Handle that while keeping most of the code
> common.

> -#define OCELOT_IF_SI_OWNER_MASK			GENMASK(5, 4)

> +			   0x3 << if_si_owner_offset,

Perhaps,

#define MSCC_IF_SI_OWNER_MASK		GENMASK(1, 0)

...

	MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,


-- 
With Best Regards,
Andy Shevchenko



----- End forwarded message -----

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2018-08-30 10:50 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-08-29 15:09 [andriy.shevchenko@linux.intel.com: Re: [PATCH] spi: dw-mmio: add MSCC Jaguar2 support] Andy Shevchenko
2018-08-29 15:15 ` Mark Brown
2018-08-29 16:52   ` Andy Shevchenko
2018-08-29 18:02   ` Alexandre Belloni
2018-08-30 10:50     ` Mark Brown

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