From mboxrd@z Thu Jan 1 00:00:00 1970 From: Corentin Labbe Subject: [PATCH v4 07/13] ata: ahci_sunxi: Bypass PHY init when using the new binding Date: Thu, 30 Aug 2018 21:01:14 +0200 Message-ID: <20180830190120.722-8-clabbe.montjoie@gmail.com> References: <20180830190120.722-1-clabbe.montjoie@gmail.com> Reply-To: clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20180830190120.722-1-clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: axboe-tSWWG44O7X1aa/9Udqfwiw@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, kishon-l0cyMroinI0@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org The new binding split sata in two (ahci + PHY). ahci_sunxi must not mess with PHY when the new binding is in use. So when we detect sub-nodes, bypass the PHY init code. This is a temporarly workaround for the period where DT and ata code will be merged from separate tree. When both new binding and PHY driver will be merged, a new patch which remove all PHY code from ahci_sunxi.c will be sent. Signed-off-by: Corentin Labbe --- drivers/ata/ahci_sunxi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c index 631610b72aa5..a09d189c6dda 100644 --- a/drivers/ata/ahci_sunxi.c +++ b/drivers/ata/ahci_sunxi.c @@ -96,6 +96,15 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) u32 reg_val; int timeout; + /* + * When using the new binding, the presence of a sata port node + * means that PHY is handled by the PHY driver. + * */ + if (of_get_child_count(dev->of_node)) { + dev_info(dev, "Bypassing PHY init\n"); + return 0; + } + /* This magic is from the original code */ writel(0, reg_base + AHCI_RWCR); msleep(5); -- 2.16.4