[PATCH 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[PATCH 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[Ivan T. Ivanov]

Following set of patches add initial DT support for PMIC devices
found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
could be found here [1].

Regards,
Ivan

[1] http://lwn.net/Articles/564637/

Ivan T. Ivanov (3):
  ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974
  ARM: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes
  ARM: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes

 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts        |  2 ++
 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts            |  1 +
 arch/arm/boot/dts/qcom-apq8084-mtp.dts                |  1 +
 arch/arm/boot/dts/qcom-apq8084.dtsi                   | 16 ++++++++++++++++
 arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts |  2 ++
 arch/arm/boot/dts/qcom-msm8974.dtsi                   | 16 ++++++++++++++++
 arch/arm/boot/dts/qcom-pm8841.dtsi                    | 18 ++++++++++++++++++
 arch/arm/boot/dts/qcom-pm8941.dtsi                    | 18 ++++++++++++++++++
 arch/arm/boot/dts/qcom-pma8084.dtsi                   | 18 ++++++++++++++++++
 9 files changed, 92 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-pm8841.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-pm8941.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-pma8084.dtsi

--
1.9.1

[PATCH 2/3] ARM: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes

[Ivan T. Ivanov]

PM8841 and PM8941 have 2 SPMI devices per physical package.
Add their configuration nodes and include them in boards
which are using 8x74 based chipset.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
---
 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts        |  2 ++
 arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts |  2 ++
 arch/arm/boot/dts/qcom-pm8841.dtsi                    | 18 ++++++++++++++++++
 arch/arm/boot/dts/qcom-pm8941.dtsi                    | 18 ++++++++++++++++++
 4 files changed, 40 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-pm8841.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-pm8941.dtsi

diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 4737049..d484d08 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -1,4 +1,6 @@
 #include "qcom-msm8974.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"

 / {
 	model = "Qualcomm APQ8074 Dragonboard";
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
index cccc21b..bd35b06 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
@@ -1,4 +1,6 @@
 #include "qcom-msm8974.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"

 / {
 	model = "Sony Xperia Z1";
diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi
new file mode 100644
index 0000000..73813cc
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -0,0 +1,18 @@
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+	usid4: pm8841@4 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x4 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	usid5: pm8841@5 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
new file mode 100644
index 0000000..24c5088
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -0,0 +1,18 @@
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+	usid0: pm8941@0 {
+		compatible ="qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	usid1: pm8941@1 {
+		compatible ="qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
--
1.9.1

[PATCH 3/3] ARM: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes

[Ivan T. Ivanov]

PMA8084 have 2 SPMI devices per physical package. Add their
configuration nodes and include them in boards which are using
AQP8084 based chipset.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
---
 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts |  1 +
 arch/arm/boot/dts/qcom-apq8084-mtp.dts     |  1 +
 arch/arm/boot/dts/qcom-pma8084.dtsi        | 18 ++++++++++++++++++
 3 files changed, 20 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-pma8084.dtsi

diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index c9ff108..f7725b9 100644
--- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -1,4 +1,5 @@
 #include "qcom-apq8084.dtsi"
+#include "qcom-pma8084.dtsi"

 / {
 	model = "Qualcomm APQ8084/IFC6540";
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
index 8ecec58..cb43acf 100644
--- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -1,4 +1,5 @@
 #include "qcom-apq8084.dtsi"
+#include "qcom-pma8084.dtsi"

 / {
 	model = "Qualcomm APQ 8084-MTP";
diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi
new file mode 100644
index 0000000..a5a4fe6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -0,0 +1,18 @@
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+	usid0: pma8084@0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	usid1: pma8084@1 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
--
1.9.1

[PATCH 1/3] ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974

[Ivan T. Ivanov]

Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974.

Signed-off-by: Ivan T. Ivanov <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi | 16 ++++++++++++++++
 arch/arm/boot/dts/qcom-msm8974.dtsi | 16 ++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 1f130bc..dbedf64 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -226,5 +226,21 @@
 			clock-names = "core", "iface";
 			status = "disabled";
 		};
+
+		spmi_bus: spmi@fc4cf000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg-names = "core", "intr", "cnfg";
+			reg = <0xfc4cf000 0x1000>,
+			      <0xfc4cb000 0x1000>,
+			      <0xfc4ca000 0x1000>;
+			interrupt-names = "periph_irq";
+			interrupts = <0 190 0>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index e265ec1..2d11641 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -247,5 +247,21 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
+
+		spmi_bus: spmi@fc4cf000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg-names = "core", "intr", "cnfg";
+			reg = <0xfc4cf000 0x1000>,
+			      <0xfc4cb000 0x1000>,
+			      <0xfc4ca000 0x1000>;
+			interrupt-names = "periph_irq";
+			interrupts = <0 190 0>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+		};
 	};
 };
--
1.9.1

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Re: [PATCH 1/3] ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974

[Frank Rowand]

Hi Ivan,


On 02/03/15 04:17, Ivan T. Ivanov wrote:
> Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974.
> 
> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> ---
>  arch/arm/boot/dts/qcom-apq8084.dtsi | 16 ++++++++++++++++
>  arch/arm/boot/dts/qcom-msm8974.dtsi | 16 ++++++++++++++++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
> index 1f130bc..dbedf64 100644
> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
> @@ -226,5 +226,21 @@
>  			clock-names = "core", "iface";
>  			status = "disabled";
>  		};
> +
> +		spmi_bus: spmi@fc4cf000 {
> +			compatible = "qcom,spmi-pmic-arb";
> +			reg-names = "core", "intr", "cnfg";
> +			reg = <0xfc4cf000 0x1000>,
> +			      <0xfc4cb000 0x1000>,
> +			      <0xfc4ca000 0x1000>;
> +			interrupt-names = "periph_irq";
> +			interrupts = <0 190 0>;> +			qcom,ee = <0>;
> +			qcom,channel = <0>;
> +			#address-cells = <2>;
> +			#size-cells = <0>;
> +			interrupt-controller;
> +			#interrupt-cells = <4>;
> +		};
>  	};
>  };
> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
> index e265ec1..2d11641 100644
> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
> @@ -247,5 +247,21 @@
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  		};
> +
> +		spmi_bus: spmi@fc4cf000 {
> +			compatible = "qcom,spmi-pmic-arb";
> +			reg-names = "core", "intr", "cnfg";
> +			reg = <0xfc4cf000 0x1000>,
> +			      <0xfc4cb000 0x1000>,
> +			      <0xfc4ca000 0x1000>;
> +			interrupt-names = "periph_irq";

> +			interrupts = <0 190 0>;

The final value in this interrupts property means IRQ_TYPE_NONE.

A WARN_ON() was added early this year to complain about use of
IRQ_TYPE_NONE: 83a86fbb5b56 "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE", resulting in many warnings spewing
forth when I boot an APQ8074 Dragonboard.  I am trying to
determine whether the warning is overly aggressive, or whether
the IRQ TYPE is incorrectly specified for the spmi node.

The interrupt-parent for the spmi node is intc: interrupt-controller@f9000000,
which has compatible = "qcom,msm-qgic2".  I do not know the architecture
or implementation of this interrupt controller.  Is an IRQ_TYPE_NONE
valid in this case, or should a specific type be provided?

Thanks!

-Frank


> +			qcom,ee = <0>;
> +			qcom,channel = <0>;
> +			#address-cells = <2>;
> +			#size-cells = <0>;
> +			interrupt-controller;
> +			#interrupt-cells = <4>;
> +		};
>  	};
>  };
> --
> 1.9.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH 1/3] ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974

[Frank Rowand]

Hi All,

The email for Ivan is no longer valid.  Can anyone else help me with
my question?

Thanks,

Frank


On 08/31/18 15:46, Frank Rowand wrote:
> Hi Ivan,
> 
> 
> On 02/03/15 04:17, Ivan T. Ivanov wrote:
>> Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974.
>>
>> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
>> ---
>>  arch/arm/boot/dts/qcom-apq8084.dtsi | 16 ++++++++++++++++
>>  arch/arm/boot/dts/qcom-msm8974.dtsi | 16 ++++++++++++++++
>>  2 files changed, 32 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
>> index 1f130bc..dbedf64 100644
>> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
>> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
>> @@ -226,5 +226,21 @@
>>  			clock-names = "core", "iface";
>>  			status = "disabled";
>>  		};
>> +
>> +		spmi_bus: spmi@fc4cf000 {
>> +			compatible = "qcom,spmi-pmic-arb";
>> +			reg-names = "core", "intr", "cnfg";
>> +			reg = <0xfc4cf000 0x1000>,
>> +			      <0xfc4cb000 0x1000>,
>> +			      <0xfc4ca000 0x1000>;
>> +			interrupt-names = "periph_irq";
>> +			interrupts = <0 190 0>;> +			qcom,ee = <0>;
>> +			qcom,channel = <0>;
>> +			#address-cells = <2>;
>> +			#size-cells = <0>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <4>;
>> +		};
>>  	};
>>  };
>> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
>> index e265ec1..2d11641 100644
>> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
>> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
>> @@ -247,5 +247,21 @@
>>  			#address-cells = <1>;
>>  			#size-cells = <0>;
>>  		};
>> +
>> +		spmi_bus: spmi@fc4cf000 {
>> +			compatible = "qcom,spmi-pmic-arb";
>> +			reg-names = "core", "intr", "cnfg";
>> +			reg = <0xfc4cf000 0x1000>,
>> +			      <0xfc4cb000 0x1000>,
>> +			      <0xfc4ca000 0x1000>;
>> +			interrupt-names = "periph_irq";
> 
>> +			interrupts = <0 190 0>;
> 
> The final value in this interrupts property means IRQ_TYPE_NONE.
> 
> A WARN_ON() was added early this year to complain about use of
> IRQ_TYPE_NONE: 83a86fbb5b56 "irqchip/gic: Loudly complain about
> the use of IRQ_TYPE_NONE", resulting in many warnings spewing
> forth when I boot an APQ8074 Dragonboard.  I am trying to
> determine whether the warning is overly aggressive, or whether
> the IRQ TYPE is incorrectly specified for the spmi node.
> 
> The interrupt-parent for the spmi node is intc: interrupt-controller@f9000000,
> which has compatible = "qcom,msm-qgic2".  I do not know the architecture
> or implementation of this interrupt controller.  Is an IRQ_TYPE_NONE
> valid in this case, or should a specific type be provided?
> 
> Thanks!
> 
> -Frank
> 
> 
>> +			qcom,ee = <0>;
>> +			qcom,channel = <0>;
>> +			#address-cells = <2>;
>> +			#size-cells = <0>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <4>;
>> +		};
>>  	};
>>  };
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
> 
> .
> 

Re: [PATCH 1/3] ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974

[Bjorn Andersson]

On Fri 31 Aug 15:46 PDT 2018, Frank Rowand wrote:
> > +		spmi_bus: spmi@fc4cf000 {
> > +			compatible = "qcom,spmi-pmic-arb";
> > +			reg-names = "core", "intr", "cnfg";
> > +			reg = <0xfc4cf000 0x1000>,
> > +			      <0xfc4cb000 0x1000>,
> > +			      <0xfc4ca000 0x1000>;
> > +			interrupt-names = "periph_irq";
> 
> > +			interrupts = <0 190 0>;
> 
> The final value in this interrupts property means IRQ_TYPE_NONE.
> 
> A WARN_ON() was added early this year to complain about use of
> IRQ_TYPE_NONE: 83a86fbb5b56 "irqchip/gic: Loudly complain about
> the use of IRQ_TYPE_NONE", resulting in many warnings spewing
> forth when I boot an APQ8074 Dragonboard.  I am trying to
> determine whether the warning is overly aggressive, or whether
> the IRQ TYPE is incorrectly specified for the spmi node.
> 
> The interrupt-parent for the spmi node is intc: interrupt-controller@f9000000,
> which has compatible = "qcom,msm-qgic2".  I do not know the architecture
> or implementation of this interrupt controller.  Is an IRQ_TYPE_NONE
> valid in this case, or should a specific type be provided?
> 

No, IRQ_TYPE_NONE isn't valid and the WARN_ON() is reasonable.

Please change it to IRQ_TYPE_LEVEL_HIGH. And while you're at it, replace
the first 0 with GIC_SPI.


If you have more of these warnings you can most likely look at e.g.
msm8916 (arm64) to find the right flags.

Regards,
Bjorn

Re: [PATCH 1/3] ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974

[Frank Rowand]

On 08/31/18 16:01, Bjorn Andersson wrote:
> On Fri 31 Aug 15:46 PDT 2018, Frank Rowand wrote:
>>> +		spmi_bus: spmi@fc4cf000 {
>>> +			compatible = "qcom,spmi-pmic-arb";
>>> +			reg-names = "core", "intr", "cnfg";
>>> +			reg = <0xfc4cf000 0x1000>,
>>> +			      <0xfc4cb000 0x1000>,
>>> +			      <0xfc4ca000 0x1000>;
>>> +			interrupt-names = "periph_irq";
>>
>>> +			interrupts = <0 190 0>;
>>
>> The final value in this interrupts property means IRQ_TYPE_NONE.
>>
>> A WARN_ON() was added early this year to complain about use of
>> IRQ_TYPE_NONE: 83a86fbb5b56 "irqchip/gic: Loudly complain about
>> the use of IRQ_TYPE_NONE", resulting in many warnings spewing
>> forth when I boot an APQ8074 Dragonboard.  I am trying to
>> determine whether the warning is overly aggressive, or whether
>> the IRQ TYPE is incorrectly specified for the spmi node.
>>
>> The interrupt-parent for the spmi node is intc: interrupt-controller@f9000000,
>> which has compatible = "qcom,msm-qgic2".  I do not know the architecture
>> or implementation of this interrupt controller.  Is an IRQ_TYPE_NONE
>> valid in this case, or should a specific type be provided?
>>
> 
> No, IRQ_TYPE_NONE isn't valid and the WARN_ON() is reasonable.
> 
> Please change it to IRQ_TYPE_LEVEL_HIGH. And while you're at it, replace
> the first 0 with GIC_SPI.
> 
> 
> If you have more of these warnings you can most likely look at e.g.
> msm8916 (arm64) to find the right flags.

Thanks, I'll create a patch.

Re: [PATCH 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[Bjorn Andersson]

On Tue, Feb 3, 2015 at 4:17 AM, Ivan T. Ivanov <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org> wrote:
> Following set of patches add initial DT support for PMIC devices
> found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
> could be found here [1].
>
> Regards,
> Ivan
>
> [1] http://lwn.net/Articles/564637/
>
> Ivan T. Ivanov (3):
>   ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974
>   ARM: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes
>   ARM: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes
>

Looks good.

Reviewed-by: Bjorn Andersson <bjorn.andersson-/MT0OVThwyLZJqsBc5GL+g@public.gmane.org>

Regards,
Bjorn
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Re: [PATCH 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[Ivan T. Ivanov]

On Tue, 2015-02-03 at 12:38 -0800, Bjorn Andersson wrote:
> On Tue, Feb 3, 2015 at 4:17 AM, Ivan T. Ivanov <iivanov@mm-sol.com> wrote:
> > Following set of patches add initial DT support for PMIC devices
> > found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
> > could be found here [1].
> > 
> > Regards,
> > Ivan
> > 
> > [1] http://lwn.net/Articles/564637/
> > 
> > Ivan T. Ivanov (3):
> >   ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974
> >   ARM: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes
> >   ARM: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes
> > 
> 
> Looks good.
> 
> Reviewed-by: Bjorn Andersson andersson@sonymobile.com>
> 

Thank you.

Any other comments? Kumar?

Regards,
Ivan

Re: [PATCH 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[Andy Gross]

On Tue, Feb 03, 2015 at 02:17:57PM +0200, Ivan T. Ivanov wrote:
> Following set of patches add initial DT support for PMIC devices
> found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
> could be found here [1].
> 

Looks fine.

Reviewed-by: Andy Gross <agross@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[Stephen Boyd]

On 02/03/15 04:17, Ivan T. Ivanov wrote:
> Following set of patches add initial DT support for PMIC devices
> found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
> could be found here [1].

Can you please put the specific compatible strings for the pmic model
into the nodes in addition to the generic "qcom,spmi-pmic"? We may want
to have regmap config tables in the future that describe the
cache/read/write abilities of the regsiters. If all we have is the
generic binding then we don't have a way to populate these tables.
Unless the plan there is to use the revid registers?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[Ivan T. Ivanov]

Hi Stephan, 

Sorry for delayed answer.

On Thu, 2015-02-19 at 16:49 -0800, Stephen Boyd wrote:
> On 02/03/15 04:17, Ivan T. Ivanov wrote:
> > Following set of patches add initial DT support for PMIC devices
> > found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
> > could be found here [1].
> 
> Can you please put the specific compatible strings for the pmic model
> into the nodes in addition to the generic "qcom,spmi-pmic"? We may want
> to have regmap config tables in the future that describe the
> cache/read/write abilities of the regsiters. If all we have is the
> generic binding then we don't have a way to populate these tables.
> Unless the plan there is to use the revid registers?
> 

I would really like that we can use "revid" registers, but I don't know... 

>From what I can see usually in one physical PMIC chip they
are 2 USID devices.

I can successfully discover following USID's on APQ8074 boards:

pmic-spmi 0-00: qcom,pm8941-v1.0 detected
pmic-spmi 0-01: qcom,pm8941-v1.0 detected
pmic-spmi 0-04: qcom,pm8841-v0.0 detected
pmic-spmi 0-05: qcom,pm8841-v0.0 detected

Unfortunately on PM8916 only one device is detected, with USID 0.
But they should be two, judging by downstream DTS files, right?

pmic-spmi 0-00: qcom,pm8916-v0.0 detected 
pmic-spmi 0-01: unknown device

For communication with PM8916 I am using recent patches from Gilad [1].
Maybe there are still some issues with these patches, which can cause
this behavior or PM8916 just didn't have these registers for USID 1?

Regards,
Ivan 

[1] https://lkml.org/lkml/2015/2/19/453

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Re: [PATCH 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[Stephen Boyd]

On 02/26, Ivan T. Ivanov wrote:
> 
> Hi Stephan, 
> 
> Sorry for delayed answer.
> 
> On Thu, 2015-02-19 at 16:49 -0800, Stephen Boyd wrote:
> > On 02/03/15 04:17, Ivan T. Ivanov wrote:
> > > Following set of patches add initial DT support for PMIC devices
> > > found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
> > > could be found here [1].
> > 
> > Can you please put the specific compatible strings for the pmic model
> > into the nodes in addition to the generic "qcom,spmi-pmic"? We may want
> > to have regmap config tables in the future that describe the
> > cache/read/write abilities of the regsiters. If all we have is the
> > generic binding then we don't have a way to populate these tables.
> > Unless the plan there is to use the revid registers?
> > 
> 
> I would really like that we can use "revid" registers, but I don't know... 
> 
> From what I can see usually in one physical PMIC chip they
> are 2 USID devices.
> 
> I can successfully discover following USID's on APQ8074 boards:
> 
> pmic-spmi 0-00: qcom,pm8941-v1.0 detected
> pmic-spmi 0-01: qcom,pm8941-v1.0 detected
> pmic-spmi 0-04: qcom,pm8841-v0.0 detected
> pmic-spmi 0-05: qcom,pm8841-v0.0 detected
> 
> Unfortunately on PM8916 only one device is detected, with USID 0.
> But they should be two, judging by downstream DTS files, right?
> 
> pmic-spmi 0-00: qcom,pm8916-v0.0 detected 
> pmic-spmi 0-01: unknown device
> 
> For communication with PM8916 I am using recent patches from Gilad [1].
> Maybe there are still some issues with these patches, which can cause
> this behavior or PM8916 just didn't have these registers for USID 1?
> 
> Regards,
> Ivan 

Hmm... do you have 4 total rev-id nodes on apq8074? I only see
one rev-id node per pmic (2 total), so I'm a little lost how the
correct pmic version is detected on the 0-01 and 0-05 devices in
your example above. Maybe I've missed something though, I'll have
to check in a few hours when I'm in the office.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[Ivan T. Ivanov]

On Tue, 2015-03-03 at 00:19 -0800, Stephen Boyd wrote:
> On 02/26, Ivan T. Ivanov wrote:
> > Hi Stephen,
> > 
> > Sorry for delayed answer.
> > 
> > On Thu, 2015-02-19 at 16:49 -0800, Stephen Boyd wrote:
> > > On 02/03/15 04:17, Ivan T. Ivanov wrote:
> > > > Following set of patches add initial DT support for PMIC devices
> > > > found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
> > > > could be found here [1].
> > > 
> > > Can you please put the specific compatible strings for the pmic model
> > > into the nodes in addition to the generic "qcom,spmi-pmic"? We may want
> > > to have regmap config tables in the future that describe the
> > > cache/read/write abilities of the regsiters. If all we have is the
> > > generic binding then we don't have a way to populate these tables.
> > > Unless the plan there is to use the revid registers?
> > > 
> > 
> > I would really like that we can use "revid" registers, but I don't know...
> > 
> > From what I can see usually in one physical PMIC chip they
> > are 2 USID devices.
> > 
> > I can successfully discover following USID's on APQ8074 boards:
> > 
> > pmic-spmi 0-00: qcom,pm8941-v1.0 detected
> > pmic-spmi 0-01: qcom,pm8941-v1.0 detected
> > pmic-spmi 0-04: qcom,pm8841-v0.0 detected
> > pmic-spmi 0-05: qcom,pm8841-v0.0 detected
> > 
> > Unfortunately on PM8916 only one device is detected, with USID 0.
> > But they should be two, judging by downstream DTS files, right?
> > 
> > pmic-spmi 0-00: qcom,pm8916-v0.0 detected
> > pmic-spmi 0-01: unknown device
> > 
> > For communication with PM8916 I am using recent patches from Gilad [1].
> > Maybe there are still some issues with these patches, which can cause
> > this behavior or PM8916 just didn't have these registers for USID 1?
> > 
> > Regards,
> > Ivan
> 
> Hmm... do you have 4 total rev-id nodes on apq8074? I only see
> one rev-id node per pmic (2 total), so I'm a little lost how the
> correct pmic version is detected on the 0-01 and 0-05 devices in
> your example above. 

Same confusion here. I am using this[1] patch to read revision info.

Address at offset 0x105 for USID 0,1 on PM8914 and USID 4,5 on PM8841
contains 0x51, which denotes them as PMIC's, so patch assumes that rest
of the registers have to contain valid version values.

Regards,
Ivan

[1] http://permalink.gmane.org/gmane.linux.kernel/1900135