From: Quentin Schulz <quentin.schulz@bootlin.com>
To: alexandre.belloni@bootlin.com, ralf@linux-mips.org,
paul.burton@mips.com, jhogan@kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, davem@davemloft.net, kishon@ti.com,
andrew@lunn.ch, f.fainelli@gmail.com
Cc: allan.nielsen@microchip.com, linux-mips@linux-mips.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org, thomas.petazzoni@bootlin.com,
Quentin Schulz <quentin.schulz@bootlin.com>
Subject: [PATCH v2 01/11] MIPS: mscc: ocelot: make HSIO registers address range a syscon
Date: Mon, 3 Sep 2018 11:32:58 +0200 [thread overview]
Message-ID: <20180903093308.24366-2-quentin.schulz@bootlin.com> (raw)
In-Reply-To: <20180903093308.24366-1-quentin.schulz@bootlin.com>
HSIO contains registers for PLL5 configuration, SerDes/switch port
muxing and a thermal sensor, hence we can't keep it in the switch DT
node.
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
---
arch/mips/boot/dts/mscc/ocelot.dtsi | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index f7eb612b46ba..149b1a7e7091 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -107,7 +107,6 @@
reg = <0x1010000 0x10000>,
<0x1030000 0x10000>,
<0x1080000 0x100>,
- <0x10d0000 0x10000>,
<0x11e0000 0x100>,
<0x11f0000 0x100>,
<0x1200000 0x100>,
@@ -121,10 +120,10 @@
<0x1280000 0x100>,
<0x1800000 0x80000>,
<0x1880000 0x10000>;
- reg-names = "sys", "rew", "qs", "hsio", "port0",
- "port1", "port2", "port3", "port4", "port5",
- "port6", "port7", "port8", "port9", "port10",
- "qsys", "ana";
+ reg-names = "sys", "rew", "qs", "port0", "port1",
+ "port2", "port3", "port4", "port5", "port6",
+ "port7", "port8", "port9", "port10", "qsys",
+ "ana";
interrupts = <21 22>;
interrupt-names = "xtr", "inj";
@@ -231,5 +230,10 @@
pinctrl-0 = <&miim1>;
status = "disabled";
};
+
+ hsio: syscon@10d0000 {
+ compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
+ reg = <0x10d0000 0x10000>;
+ };
};
};
--
2.17.1
next prev parent reply other threads:[~2018-09-03 9:32 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-03 9:32 [PATCH v2 00/11] mscc: ocelot: add support for SerDes muxing configuration Quentin Schulz
2018-09-03 9:32 ` Quentin Schulz [this message]
2018-09-03 9:32 ` [PATCH net-next v2 02/11] dt-bindings: net: ocelot: remove hsio from the list of register address spaces Quentin Schulz
2018-09-03 9:33 ` [PATCH net-next v2 03/11] net: mscc: ocelot: get HSIO regmap from syscon Quentin Schulz
2018-09-03 9:33 ` [PATCH net-next v2 04/11] net: mscc: ocelot: move the HSIO header to include/soc Quentin Schulz
2018-09-03 9:33 ` [PATCH net-next v2 05/11] net: mscc: ocelot: simplify register access for PLL5 configuration Quentin Schulz
2018-09-03 9:33 ` [PATCH v2 06/11] phy: add QSGMII and PCIE modes Quentin Schulz
2018-09-03 9:33 ` [PATCH v2 07/11] dt-bindings: phy: add DT binding for Microsemi Ocelot SerDes muxing Quentin Schulz
2018-09-03 9:33 ` [PATCH v2 08/11] MIPS: mscc: ocelot: add SerDes mux DT node Quentin Schulz
2018-09-03 9:33 ` [PATCH v2 09/11] dt-bindings: add constants for Microsemi Ocelot SerDes driver Quentin Schulz
2018-09-03 9:33 ` [PATCH v2 10/11] phy: add driver for Microsemi Ocelot SerDes muxing Quentin Schulz
2018-09-03 9:33 ` [PATCH net-next v2 11/11] net: mscc: ocelot: make use of SerDes PHYs for handling their configuration Quentin Schulz
2018-09-03 13:34 ` [PATCH v2 00/11] mscc: ocelot: add support for SerDes muxing configuration Andrew Lunn
2018-09-03 13:45 ` Alexandre Belloni
2018-09-04 5:09 ` David Miller
2018-09-04 15:16 ` Alexandre Belloni
2018-09-04 16:10 ` Paul Burton
2018-09-04 18:00 ` Quentin Schulz
2018-09-04 23:03 ` Paul Burton
2018-09-05 9:07 ` Alexandre Belloni
2018-09-04 17:17 ` David Miller
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