From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v4 02/11] clk: sunxi-ng: a64: Add max. rate constraint to video PLLs Date: Wed, 5 Sep 2018 09:16:45 +0200 Message-ID: <20180905071645.ibhcuq5coc6gl6k3@flea> References: <20180904044053.15425-1-icenowy@aosc.io> <20180904044053.15425-3-icenowy@aosc.io> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="dces3elbc3qktb53" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20180904044053.15425-3-icenowy-h8G6r0blFSE@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Chen-Yu Tsai , Jagan Teki , Jernej Skrabec , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org --dces3elbc3qktb53 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote: > Video PLLs on A64 can be set to higher rate that it is actually > supported by HW. > > Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP > clock driver. Interestengly, user manual specifies maximum frequency to > be 600 MHz. Historically, this data was wrong in some user manuals for > other SoCs, so more faith is put in BSP clock driver. > > Signed-off-by: Icenowy Zheng Applied, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --dces3elbc3qktb53--