From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v4 08/11] arm64: dts: allwinner: a64: Add display pipeline Date: Wed, 5 Sep 2018 09:50:56 +0200 Message-ID: <20180905075056.tob7itg3judccooe@flea> References: <20180904044053.15425-1-icenowy@aosc.io> <20180904044053.15425-9-icenowy@aosc.io> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="yi7cc75vsj32ybox" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20180904044053.15425-9-icenowy-h8G6r0blFSE@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Chen-Yu Tsai , Jagan Teki , Jernej Skrabec , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org --yi7cc75vsj32ybox Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Tue, Sep 04, 2018 at 12:40:50PM +0800, Icenowy Zheng wrote: > + hdmi_phy: hdmi-phy@1ef0000 { > + compatible = "allwinner,sun8i-h3-hdmi-phy"; > + reg = <0x01ef0000 0x10000>; > + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, > + <&ccu 7>; > + clock-names = "bus", "mod", "pll-0"; > + resets = <&ccu RST_BUS_HDMI0>; > + reset-names = "phy"; > + #phy-cells = <0>; > + }; This needs to use the bindings we have for that phy. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --yi7cc75vsj32ybox--