From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v4 08/11] arm64: dts: allwinner: a64: Add display pipeline Date: Fri, 7 Sep 2018 10:21:22 +0200 Message-ID: <20180907082122.bcylf2jpf6eq6dgq@flea> References: <20180904044053.15425-1-icenowy@aosc.io> <20180904044053.15425-9-icenowy@aosc.io> <20180905075056.tob7itg3judccooe@flea> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="oztiuxukmzniiijw" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Jagan Teki Cc: Icenowy Zheng , Chen-Yu Tsai , Jernej Skrabec , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk , linux-sunxi List-Id: devicetree@vger.kernel.org --oztiuxukmzniiijw Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Fri, Sep 07, 2018 at 09:43:29AM +0530, Jagan Teki wrote: > On Wed, Sep 5, 2018 at 1:20 PM, Maxime Ripard wrote: > > On Tue, Sep 04, 2018 at 12:40:50PM +0800, Icenowy Zheng wrote: > >> + hdmi_phy: hdmi-phy@1ef0000 { > >> + compatible = "allwinner,sun8i-h3-hdmi-phy"; > >> + reg = <0x01ef0000 0x10000>; > >> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, > >> + <&ccu 7>; > >> + clock-names = "bus", "mod", "pll-0"; > >> + resets = <&ccu RST_BUS_HDMI0>; > >> + reset-names = "phy"; > >> + #phy-cells = <0>; > >> + }; > > > > This needs to use the bindings we have for that phy. > > You mean allwinner,sun50i-a64-hdmi-phy ? Yes Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --oztiuxukmzniiijw--