From: Simon Horman <horms@verge.net.au>
To: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Rob Herring <robh+dt@kernel.org>,
Geert Uytterhoeven <geert@linux-m68k.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] ARM: dts: r9a06g032: Correct UART and add all other UARTs
Date: Fri, 14 Sep 2018 15:36:01 +0200 [thread overview]
Message-ID: <20180914133600.nhbgbmxiafc65abw@verge.net.au> (raw)
In-Reply-To: <20180912092035.lhzlebd6rh72yjgj@verge.net.au>
On Wed, Sep 12, 2018 at 11:20:39AM +0200, Simon Horman wrote:
> On Mon, Sep 10, 2018 at 05:02:54PM +0100, Phil Edworthy wrote:
> > - UART0 was missing the bus clock ("apb_pclk").
> > - Now that the relevant rzn1 bindings have been added, replace the Synopsys
> > compat string with the rzn1 strings.
>
> Perhaps: Use recently accepted r9a06g032 and rzn1 compat strings.
>
> > - Add all the other UARTs.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
>
> The above notwithstanding this looks good to me but I will wait to see if
> there are other reviews before applying.
>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Thanks again, I have applied this for v4.20 with the changelog
update above.
prev parent reply other threads:[~2018-09-14 13:36 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-10 16:02 [PATCH v2] ARM: dts: r9a06g032: Correct UART and add all other UARTs Phil Edworthy
2018-09-12 9:20 ` Simon Horman
2018-09-14 13:36 ` Simon Horman [this message]
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