From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Joerg Roedel <joro@8bytes.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 09/21] memory: tegra: Adapt to Tegra20 device-tree binding changes
Date: Mon, 1 Oct 2018 01:48:21 +0300 [thread overview]
Message-ID: <20180930224833.28809-10-digetx@gmail.com> (raw)
In-Reply-To: <20180930224833.28809-1-digetx@gmail.com>
The tegra20-mc device-tree binding has been changed, GART has been
squashed into Memory Controller and now the clock property is mandatory
for Tegra20, the DT compatible has been changed as well. Adapt driver to
the DT changes.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/memory/tegra/mc.c | 21 ++++++++-------------
drivers/memory/tegra/mc.h | 6 ------
include/soc/tegra/mc.h | 2 +-
3 files changed, 9 insertions(+), 20 deletions(-)
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index e56862495f36..1b4ceefd82f9 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -51,7 +51,7 @@
static const struct of_device_id tegra_mc_of_match[] = {
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- { .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
+ { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
@@ -638,24 +638,19 @@ static int tegra_mc_probe(struct platform_device *pdev)
if (IS_ERR(mc->regs))
return PTR_ERR(mc->regs);
+ mc->clk = devm_clk_get(&pdev->dev, "mc");
+ if (IS_ERR(mc->clk)) {
+ dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
+ PTR_ERR(mc->clk));
+ return PTR_ERR(mc->clk);
+ }
+
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
if (mc->soc == &tegra20_mc_soc) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- mc->regs2 = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(mc->regs2))
- return PTR_ERR(mc->regs2);
-
isr = tegra20_mc_irq;
} else
#endif
{
- mc->clk = devm_clk_get(&pdev->dev, "mc");
- if (IS_ERR(mc->clk)) {
- dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
- PTR_ERR(mc->clk));
- return PTR_ERR(mc->clk);
- }
-
err = tegra_mc_setup_latency_allowance(mc);
if (err < 0) {
dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index 01065f12ebeb..9856f085e487 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -26,18 +26,12 @@
static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
{
- if (mc->regs2 && offset >= 0x24)
- return readl(mc->regs2 + offset - 0x3c);
-
return readl(mc->regs + offset);
}
static inline void mc_writel(struct tegra_mc *mc, u32 value,
unsigned long offset)
{
- if (mc->regs2 && offset >= 0x24)
- return writel(value, mc->regs2 + offset - 0x3c);
-
writel(value, mc->regs + offset);
}
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index b43f37fea096..db5bfdf589b4 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -144,7 +144,7 @@ struct tegra_mc_soc {
struct tegra_mc {
struct device *dev;
struct tegra_smmu *smmu;
- void __iomem *regs, *regs2;
+ void __iomem *regs;
struct clk *clk;
int irq;
--
2.19.0
next prev parent reply other threads:[~2018-09-30 22:48 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-30 22:48 [PATCH v5 00/21] IOMMU: Tegra GART driver clean up and optimization Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 01/21] iommu/tegra: gart: Remove pr_fmt and clean up includes Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 02/21] iommu/tegra: gart: Clean up driver probe errors handling Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 03/21] iommu/tegra: gart: Ignore devices without IOMMU phandle in DT Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 04/21] iommu: Introduce iotlb_sync_map callback Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 05/21] iommu/tegra: gart: Optimize mapping / unmapping performance Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 06/21] dt-bindings: memory: tegra: Squash tegra20-gart into tegra20-mc Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 07/21] ARM: dts: tegra20: Update Memory Controller node to the new binding Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 08/21] memory: tegra: Don't invoke Tegra30+ specific memory timing setup on Tegra20 Dmitry Osipenko
2018-09-30 22:48 ` Dmitry Osipenko [this message]
2018-09-30 22:48 ` [PATCH v5 10/21] memory: tegra: Read client ID on GART page fault Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 11/21] memory: tegra: Use of_device_get_match_data() Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 12/21] memory: tegra: Use relaxed versions of readl/writel Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 13/21] iommu/tegra: gart: Integrate with Memory Controller driver Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 14/21] iommu/tegra: gart: Fix spinlock recursion Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 15/21] iommu/tegra: gart: Fix NULL pointer dereference Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 16/21] iommu/tegra: gart: Allow only one active domain at a time Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 17/21] iommu/tegra: gart: Don't use managed resources Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 18/21] iommu/tegra: gart: Prepend error/debug messages with "gart:" Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 19/21] iommu/tegra: gart: Don't detach devices from inactive domains Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 20/21] iommu/tegra: gart: Simplify clients-tracking code Dmitry Osipenko
2018-09-30 22:48 ` [PATCH v5 21/21] iommu/tegra: gart: Perform code refactoring Dmitry Osipenko
[not found] ` <20180930224833.28809-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-16 12:13 ` [PATCH v5 00/21] IOMMU: Tegra GART driver clean up and optimization Dmitry Osipenko
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