From: Sudeep Holla <sudeep.holla@arm.com>
To: Wendy Liang <wendy.liang@xilinx.com>
Cc: jassisinghbrar@gmail.com, michal.simek@xilinx.com,
robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
Date: Wed, 10 Oct 2018 10:57:41 +0100 [thread overview]
Message-ID: <20181010095741.GA14472@e107155-lin> (raw)
In-Reply-To: <1539155912-29760-3-git-send-email-wendy.liang@xilinx.com>
On Wed, Oct 10, 2018 at 12:18:32AM -0700, Wendy Liang wrote:
> Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
> in ZynqMP SoC used for the communication between various processor
> systems.
>
> Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
[...]
> +Optional properties:
> +--------------------
> +- method: The method of accessing the IPI agent registers.
> + Permitted values are: "smc" and "hvc". Default is
> + "smc".
You are mixing the hardware messaging based mailbox and the software
"smc/hvc" based mailbox together here. Please keep them separated.
IIUC smc/hvc based mailcox is used for "tx" or too keep it simple in
one direction and hardware based is used for "rx" or the other direction
for communication.
You *should not* mix them as single unit. Also lots of other vendor need
SMC/HVC based mailbox. So make it generic and keep it separate.
--
Regards,
Sudeep
next prev parent reply other threads:[~2018-10-10 9:57 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-10 7:18 [PATCH v4 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver Wendy Liang
2018-10-10 7:18 ` [PATCH v4 1/2] mailbox: ZynqMP IPI mailbox controller Wendy Liang
2018-10-10 7:18 ` [PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox Wendy Liang
2018-10-10 9:57 ` Sudeep Holla [this message]
2018-10-10 22:53 ` Wendy Liang
2018-10-29 18:01 ` Jiaying Liang
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